Chungan Peng

An Efficient VLSI Implementation of Distributed Architecture for DWT

This paper proposes an efficient and simple architecture for 9/7 discrete wavelet transform based on distributed arithmetic. To derive new proposed architecture, we consider the periodicity and symmetry of DWT to optimize the performance and reduce the computational redundancy. The inner product of coefficient matrix of DWT is distributed over the input by careful analysis of input, output and coefficient word lengths. In the coefficient matrix, linear maps are used to assign the necessary computation to processing elements in space domain. Moreover, the proposed architecture has regular data flow, and low control complexity. The result is a low hardware complexity DWT processor for 9/7 transforms, which allows two times faster clock than the direct implementation. This design is very suitable for image compression systems, e.g., JPEG2000 and MPEG4

The implementation methods of high speed FIR filter on FPGA

This paper implements a sixteen-order high-speed Finite Impose Response (FIR) filter with four different popular methods: Conventional multiplications and additions; Full custom Distributed Arithmetic (DA) scheme; Add-and-Shift method with advanced calculation schedule. Each scheme is analyzed in detail including implementing process and advantages and/or drawbacks in order to present a practical reference. All of these implementations are aimed to implement on Xilinx Spartan 3 devices and we also compare our results with an industry result produced by Xilinx CoregenTM also using Distributed Arithmetic. The premium add-and-shift method observes up to 80% reduction in total occupied slices and 63.3% versus the largest conventional parallel multiplication implementation.

An Area Efficient High Performance DCT Distributed Architecture for Video Compression

Discrete cosine transform (DCT), which is an important component of image and video compression, is adopted in various standardized coding schemes, such as JPEG, MPEGx and H.26x. But when compute a two-dimensional (2D) DCT, a large number of multiplications and additions are required in the direct approach. Multiplications, which are the most time-consuming operations in simple processor, can be completely avoided in the proposed architecture for real-time image compression. An area efficient high performance VLSI architecture for DCT based on the distributed arithmetic is proposed in this paper. Minimum number of additions is used to the DCT by exploiting the timing property of the DCT transform based on the distributed arithmetic. A case study of 8 times 8 DCT architecture based on the DA is analyzed. Savings exceeding 97% are achieved for the DCT implementation.

A Memory-Efficient CAVLC Decoding Scheme for H.264/AVC

This paper presents a memory-efficient CAVLC decoding architecture for H.264/AVC. In the proposed architecture, not only the memory space is reduced for decoding the syntax elements such as coeff token, total zero, and run before, but also the decode efficiency is improved. After the analysis of the decoding principle of the CAVLC, we simplify the coeff-token VLD table and propose a new coeff-token VLD based on arithmetic operation and the look-up table combination architecture. The run-before VLD can used the same principle as the proposed coeff-token VLD. Otherwise, the proposed scheme also adope the zero block skipping technique and multiple symbols decoding scheme when decoding SignTrail. The simulation results show that our system can run at I68MHz clock frequency and the average cycles for decoding one macro-block is 136 cycles. The proposed architecture can achieves an approximate 39-53% savings in memory access without video quality degrading.

Efficient VLSI Design and Implementation of Integer Motion Estimation for H.264 SDTV Encoder

In this paper, the VLSI hardware complexity for H.264 integer motion estimation is analyzed, several hardware-reduction techniques are investigated and a Sot-SAD-Tree VLSI structure based on SAD-Tree is proposed. Using this Sot-SAD-Tree structure, the whole data path width is reduced to 50%, and the H.264 encoder with large frame and complex motion vector can be VLSI implementation with acceptable hardware cost. Finally, a complete H.264 SDTV integer motion estimation VLSI architecture with 16times256 parallelism is designed and implemented

A novel H.264 QP adaptive MPDC block-matching algorithm and its VLSI design

The computational complexity and hardware design of block-matching criteria were discussed, and a novel MPDC algorithm and its VLSI structure for H.264 were presented, in which a QP adaptive MPDC threshold was derived from the basics of H.264 4×4 integer transform and 52-level scalar quantization and the calculation process was adjusted for hardware optimization. When QP is greater than 18, the proposed criterion performs as well as SAD scheme, and the RDO curve error is less than 0.3 dB. Verilog HDL and SYNOPSYS DC-Shell are used for its VLSI design and implementation, and the synthesis results show that its 4 × 4 block-parallel structure saves 58% area and 77% power comparing with that of SAD¿s at 200 MHz. It is useful for some high-compression-ratio, low-cost and low-power video codec VLSI solutions.

An acquisition circuit in Global Positioning System receivers

The conventional matched filter structures are investigated in this paper. An acquisition circuit based on the polyphase form matched filter in Global Positioning System (GPS) receiver is provided. At the cost of less hardware resource, the significant advantage in the speed of synchronization is offered. For 32×128 polyphase form matched filter, the critical path delay approximately reduces 1/2, the sample frequency would be double.

A VLSI structural optimization method and workflow based on synthesis frequency inflexion

A synthesis frequency inflexion phenomenon of VLSI synthesis process is discussed, and then a VLSI structural optimization method with its workflow based on the analysis of synthesis frequency infrexion and register insertion is proposed. Registers are usually used for sequential synchronization and increasing maximum operating frequency, but in this issue, they are utilized to avoid excessively high combinational logic expenditure. In the H.264 macroblock-level SAD tree case, 50.6% improvement in speed is achieved at the expense of 2.9% increment in area. This method contains no complex algorithm, but exhibits good operability and generality. It is very suitable and useful for complicated VLSI structural design and/or their critical path optimization.