Dunshan Yu

An Efficient VLSI Implementation of Distributed Architecture for DWT

This paper proposes an efficient and simple architecture for 9/7 discrete wavelet transform based on distributed arithmetic. To derive new proposed architecture, we consider the periodicity and symmetry of DWT to optimize the performance and reduce the computational redundancy. The inner product of coefficient matrix of DWT is distributed over the input by careful analysis of input, output and coefficient word lengths. In the coefficient matrix, linear maps are used to assign the necessary computation to processing elements in space domain. Moreover, the proposed architecture has regular data flow, and low control complexity. The result is a low hardware complexity DWT processor for 9/7 transforms, which allows two times faster clock than the direct implementation. This design is very suitable for image compression systems, e.g., JPEG2000 and MPEG4

Low power adiabatic logic based on FinFETs

With the aggressive scaling of device technology, the leakage power has become the main part of power consumption, which seriously reduces the energy recovery efficiency of adiabatic logic. In this paper, a novel low-power adiabatic logic based on FinFET devices has been proposed. Due to the lower leakage current, higher on-state current and design flexibility of FinFETs, the proposed adiabatic logic shows considerable power reduction, performance improvement and area saving compared with CMOS adiabatic logic. An 8-state clock chain as the test circuit has been demonstrated based on the 32-nm FinFET Predictive Technology Model. The simulation results show that adiabatic circuit based on FinFET devices achieves a power reduction of up to 84.8% and a limiting frequency of up to 55 GHz.

Design and implementation of a parallel real-time FFT processor

More and more communication systems call for an efficient FFT component. This paper implements a real-time FFT processor that performs 1 K point FFT, and, with our strategy, we realize a 16 K point FFT processor by only enlarging the memories and counter in the controller. Finally, we implemented an FFT processor with a Xilinx VirtexII FPGA, which can perform 1 K, 2 K, 4 K, 8 K and 16 K, respectively, corresponding to the external configuration. The system clock is 50 MHz, which means that our FFT processor can accomplish a 16 K complex point FFT in 40 ns.

The implementation methods of high speed FIR filter on FPGA

This paper implements a sixteen-order high-speed Finite Impose Response (FIR) filter with four different popular methods: Conventional multiplications and additions; Full custom Distributed Arithmetic (DA) scheme; Add-and-Shift method with advanced calculation schedule. Each scheme is analyzed in detail including implementing process and advantages and/or drawbacks in order to present a practical reference. All of these implementations are aimed to implement on Xilinx Spartan 3 devices and we also compare our results with an industry result produced by Xilinx CoregenTM also using Distributed Arithmetic. The premium add-and-shift method observes up to 80% reduction in total occupied slices and 63.3% versus the largest conventional parallel multiplication implementation.

Digital OFDM transmitter architecture and FPGA design

OFDM technology is an effective multicarrier technology and is the key technology of HiNOC physical layer standard. In this paper, a digital OFDM transmitter architecture is studied and designed. At system level, algorithm model is constructed with MATLAB. At circuit level, the main function modules such as a 256-point IFFT processor are presented considering implementation complexity. At last, the OFDM transmitter is implemented with ALTERA StratixII FPGA. The testing result shows that transmitter function is correct and performance meets design requirement perfectly1.

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs

With the technology scaling down, low power dissipation has become one of the research focuses in the field of integrated circuit design. Various types of adiabatic logics have been invented for low-power applications. However, the expanding leakage current degrades the performance of conventional adiabatic logics. In this article, a novel improved complementary pass-transistor adiabatic logic (ICPAL) based on fin-type field-effect transistor (FinFET) devices with ultra-low power dissipation has been presented. The proposed ICPAL takes full advantage of different FinFET operating modes, that is, shorted-gate mode, independent-gate mode, and low-power mode, to make a tremendous reduction in power dissipation. For explication and verification, the power dissipation of different ICPAL standard cells has been investigated and compared with other types of adiabatic circuits based on FinFETs. The results show that the ICPAL circuits have ultra-low power dissipation in a wide range of clock frequencies(30–800 MHz) under the condition of similar number of transistors, and the average reduction in power dissipation is about 23.1%, 75.0%, and 50.0% relative to 2N-2N2P, improved pass-transistor adiabatic logic, and complimentary pass-transistor adiabatic logic, respectively. Furthermore, ICPAL supports a better pre-evaluation of system power dissipation in VLSI design and has an intrinsic characteristic for the resistance to some types of side channel attacks.

Key characterization factors of accurate power modeling for FinFET circuits

Due to its excellent device features, manufacture process compatibility and diversity of the circuit structures, The FinFET is considered appropriate candidate for the conventional bulk-MOSFET in sub-22nm technology nodes. However, the power estimation CAD tools for FinFET are missing at the moment, which mainly results from the absence of FinFET power analysis and FinFET power model. Three key factors for FinFET power model are: the dimension of the look-up-tables, that to find out the most significant factors that influence FinFET power and to make them as indexes for the look-up-tables; the distance between sampling points; and the interpolation method. In this paper, various factors that may contribute to the FinFET power consumption are evaluated. Of all the factors, the continuous ones are compared with sensitivity method. As to other discrete factors, methods of building them in power model are given according to the features of the each factor and the way it influences the power. Based on the simulation result, standard cell power library model for FinFET is proposed. The research work lays foundation for accurate power analysis and modeling for high-level power analysis of FinFET circuits. Besides, these key factors are also crucial for low-power FinFET circuit design.摘要创新点FinFET由于具有良好的器件特性、制程兼容性和多种电路结构, 被认为是在22nm以下制程工艺中替代传统体硅MOSFET最有效的器件。 然而, 针对FinFET的功耗分析在现阶段仍然缺失。 本文针对FinFET不同的电路结构特点, 采用PTM 32nm FinFETs模型在HSpice上进行了详尽的功耗来源与影响因素分析: 针对电路连接模式、背栅电压、输入信号歪斜、输出电容负载、电路输入状态、以前的状态、时序动作、温度等一些可能对功耗造成影响的因素进行了一一探讨。 需要特别关注的是, 与体硅MOSFET相比, 双栅FinFET器件的阈值电压增加了一个背栅电压的控制量, 本文针对这一FinFET特点进行了着重探讨。 通过量化和比较所有的功耗影响因素, 改进了已有的功耗库模型。 本文对于低功耗设计人员与CAD软件设计人员具有指导和借鉴意义。

A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs

In this paper, a novel device/circuit co-design scheme, namely Dynamic-Adjusting Threshold-Voltage Scheme (DATS) for independent-gate mode FinFET circuits has been proposed. The main idea of this scheme is that a pair of back-gate bias of FinFETs is adjusted dynamically to change threshold voltage according to the system operating frequency and operating mode, which could optimize circuit power, especially leakage power. The experimental and simulation result shows that the leakage power dissipation reduced greatly when circuits operate at the lower frequency, and the energy-delay product of FinFET circuits is reduced by 30% approximately.

A control and readout circuit with capacitive mismatch auto-compensation for MEMS vibratory gyroscope

In this paper, a control and readout circuit for MEMS vibratory gyroscope is described, including closed- loop driving axis and open-loop sensing axis. Capacitive mismatch auto-compensation has been implemented in this system to suppress the influence to the output due to the mismatch of gyroscope capacitors. The ASIC is fabricated in a 0.35um CMOS process. The test of the ASIC is performed with a MEMS vibratory gyroscope. The test result shows that the non-linearity is less than 0.1% within angular velocity range of -300°/s to 300°/s.

A parallel intra prediction architecture for H.264 video decoding

In this paper, an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 video coding standard is adopted. The hardware design is based on a novel organization of the intra prediction equations. Compared with conventional architecture, intra predict efficiency is enhanced. The Verilog RTL is verified to work at 103 MHz in a Xilinx II FPGA1.