Shimin Sheng

A CORDIC Demodulator Platform for Digital-IF Receiver

A reconfigurable CORDIC demodulator platform and design method for digital-IF receiver is presented. A 2-level FSK demodulator for family network is implemented and tested on that platform with Xilinx VirtexII XC2V1000-4FG256 FPGA. The 2-level FSK noncoherent detector is designed based on counting the zero crossing points using new noise elimination technique. Synchronization control information is extracted from the amplitude signal through setting protection parameters. The output BER is 0.01% for input SNR of 1dB with frequency offset of 0.1MHz

A Pipelined Interpolating Analog-to-Digital Converter with Reduced Nonlinearity Error

An interpolating analog-to-digital converter (ADC) using pipelined architecture is designed. In order to obtain a high linearity of the ADC, a differential difference amplifier (DDA) with well restrained nonlinearity error is adopted to reduce the nonlinearity error. Furthermore, a latched comparator is proposed to achieve a low kickback noise, which is of great importance to the linearity of the ADC. The ADC is implemented in a 0.35 mum standard digital CMOS process with a single 3.3 V supply, and achieves 8 bit resolution at speeds up to 50 MSamples/s.

Efficient VLSI Design and Implementation of Integer Motion Estimation for H.264 SDTV Encoder

In this paper, the VLSI hardware complexity for H.264 integer motion estimation is analyzed, several hardware-reduction techniques are investigated and a Sot-SAD-Tree VLSI structure based on SAD-Tree is proposed. Using this Sot-SAD-Tree structure, the whole data path width is reduced to 50%, and the H.264 encoder with large frame and complex motion vector can be VLSI implementation with acceptable hardware cost. Finally, a complete H.264 SDTV integer motion estimation VLSI architecture with 16times256 parallelism is designed and implemented

A novel H.264 QP adaptive MPDC block-matching algorithm and its VLSI design

The computational complexity and hardware design of block-matching criteria were discussed, and a novel MPDC algorithm and its VLSI structure for H.264 were presented, in which a QP adaptive MPDC threshold was derived from the basics of H.264 4×4 integer transform and 52-level scalar quantization and the calculation process was adjusted for hardware optimization. When QP is greater than 18, the proposed criterion performs as well as SAD scheme, and the RDO curve error is less than 0.3 dB. Verilog HDL and SYNOPSYS DC-Shell are used for its VLSI design and implementation, and the synthesis results show that its 4 × 4 block-parallel structure saves 58% area and 77% power comparing with that of SAD¿s at 200 MHz. It is useful for some high-compression-ratio, low-cost and low-power video codec VLSI solutions.

Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm

A 2-level FSK digital modems with CORDIC algorithm for family network is presented. The noncoherent detector is designed based on counting the zero crossings using new noise elimination technique. Synchronization control information is extracted from the magnitude signal through setting protection parameters. The output BER is 0.01% for input SNR of 1dB with frequency offset of 0.1MHz. The design is implemented with Xilinx VirtexII XC2V1000-4FG256 FPGA

A behavior-oriented simulation tool for design and optimization of sigma-delta ADCs

In this paper, a behavior-oriented simulation tool is proposed for the designing and optimizing of sigma-delta ADCs. We show how this kind of simulation tool can be used in a top-down design flow in the mixed-signal system design. The imperfections of the analog cells as integrators, comparator, and the CpAMPs are analyzed in detail, which guides the design towards high performance. Besides, the modeling, simulation, and design of a second-order sigma-delta modulator are presented as a proof for the effectiveness of the simulation tool. A peak SNR of 91.5 dB, a 15 bit resolution, and a 57 m W power dissipation are obtained through HSPICE simulation. Currently chip is in the fabrication phase.

Delay Line Encoding For Low Power

This paper proposed a delay line encoding approach for low power. The encoding method is based on word-level statistical properties of the data. Functional characters were simulated by MATLAB, and the corresponding hardware was implemented in SMIC 0.18mum digital library. The two implementation for on-chip delay lines, DFF based and memory based are both analyzed in this paper. Gate-level properties are discussed in detail for different circumstances

A High Performance and Low Power Hardware Architecture of Entropy Coder for H.264/AVC Baseline

In this paper, the authors present a high performance and low power hardware architecture of entropy coder for H.264/AVC baseline. The authors implemented the architecture with SYNOPSYS design compiler and SMIC 0.13mum cell library. The result shows that the design need less area than the prior work and it can work at frequency 250Hz. In the worst case, it needs 1095 circles to code a macro block and can process 2306 QCIF (176times144) frames per second

A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs

In this paper, the nonlinearity error induced by interpolation amplifier in interpolating analog-to-digital converters (ADCs) is analyzed, and a new differential difference amplifier (DDA) with well restrained nonlinearity error is presented. Its highly steady common-mode output voltage makes it especially suitable for differential interpolating ADCs. The amplifier is designed in a 0.35mum standard CMOS process with a single 3.3V supply. Simulated results show that this amplifier achieves a steady common-mode output in a wide common-mode input range from 0.85V to 2.45V without demanding complex circuitry. The amplifier settles in 4.8ns to an accuracy of 0.01% and dissipates a total power of 398.38muW

Design and Implementation of Digital Up Converter for Homenet

Based on the classical system design flow, a custom digital up converter (DUC) IP is designed and implemented for Homenet system. At the system level, DUC behavior model is constructed and DUC system architecture, spectra distribution scheme and circuit parameters are confirmed with system modeling tool MATLAB. At the circuit level, the main function modules such as interpolator and numerically controlled oscillators (NCO) and so on are designed and implemented. Considering the limited hardware resources and performance specification, a large number of optimizing technologies and algorithm are adopted. At last, Homenet system verification flat including our custom digital up converter system is realized with Xilinx Virtexll XC2V1000-4FG256 FPGA.