Xiaoxin Cui

Low power adiabatic logic based on FinFETs

With the aggressive scaling of device technology, the leakage power has become the main part of power consumption, which seriously reduces the energy recovery efficiency of adiabatic logic. In this paper, a novel low-power adiabatic logic based on FinFET devices has been proposed. Due to the lower leakage current, higher on-state current and design flexibility of FinFETs, the proposed adiabatic logic shows considerable power reduction, performance improvement and area saving compared with CMOS adiabatic logic. An 8-state clock chain as the test circuit has been demonstrated based on the 32-nm FinFET Predictive Technology Model. The simulation results show that adiabatic circuit based on FinFET devices achieves a power reduction of up to 84.8% and a limiting frequency of up to 55 GHz.

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias

Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk noise between the neighboring TSVs, and result in the extra delay and the deterioration of signal integrity. For a

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs

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Key characterization factors of accurate power modeling for FinFET circuits

TSV array, the severity of crosstalk noise in the center victim TSV is classified into 11 levels, which is defined as 0C to 10C from low noise to high noise, depending on the combinations of the digital patterns applied to the TSV array. An enhanced code based on the Fibonacci number system (FNS) to suppress the crosstalk noise below 6C level is proposed, in which both the redundancy of numbers and the nonuniqueness of Fibonacci-based binary codeword are utilized to search the proper codeword. Experimental results show that the proposed technique decreases about 22% latency of TSVs comparing with the worst crosstalk cases. This technique is applicable in the large-scale TSV array for it has a quasi-linear hardware overhead, and its system overhead is less than that of the 3-D 4-LAT counterpart if the data width is greater than 18, and it has good usability for it consumes less power per TSV and achieves lower bit error rate at the interested frequency range comparing with that of the original FNS coding technique.

A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs

With the technology scaling down, low power dissipation has become one of the research focuses in the field of integrated circuit design. Various types of adiabatic logics have been invented for low-power applications. However, the expanding leakage current degrades the performance of conventional adiabatic logics. In this article, a novel improved complementary pass-transistor adiabatic logic (ICPAL) based on fin-type field-effect transistor (FinFET) devices with ultra-low power dissipation has been presented. The proposed ICPAL takes full advantage of different FinFET operating modes, that is, shorted-gate mode, independent-gate mode, and low-power mode, to make a tremendous reduction in power dissipation. For explication and verification, the power dissipation of different ICPAL standard cells has been investigated and compared with other types of adiabatic circuits based on FinFETs. The results show that the ICPAL circuits have ultra-low power dissipation in a wide range of clock frequencies(30–800 MHz) under the condition of similar number of transistors, and the average reduction in power dissipation is about 23.1%, 75.0%, and 50.0% relative to 2N-2N2P, improved pass-transistor adiabatic logic, and complimentary pass-transistor adiabatic logic, respectively. Furthermore, ICPAL supports a better pre-evaluation of system power dissipation in VLSI design and has an intrinsic characteristic for the resistance to some types of side channel attacks.

A 2-Level FSK Demodulator for Digital-IF Receiver

Due to its excellent device features, manufacture process compatibility and diversity of the circuit structures, The FinFET is considered appropriate candidate for the conventional bulk-MOSFET in sub-22nm technology nodes. However, the power estimation CAD tools for FinFET are missing at the moment, which mainly results from the absence of FinFET power analysis and FinFET power model. Three key factors for FinFET power model are: the dimension of the look-up-tables, that to find out the most significant factors that influence FinFET power and to make them as indexes for the look-up-tables; the distance between sampling points; and the interpolation method. In this paper, various factors that may contribute to the FinFET power consumption are evaluated. Of all the factors, the continuous ones are compared with sensitivity method. As to other discrete factors, methods of building them in power model are given according to the features of the each factor and the way it influences the power. Based on the simulation result, standard cell power library model for FinFET is proposed. The research work lays foundation for accurate power analysis and modeling for high-level power analysis of FinFET circuits. Besides, these key factors are also crucial for low-power FinFET circuit design.摘要创新点FinFET由于具有良好的器件特性、制程兼容性和多种电路结构, 被认为是在22nm以下制程工艺中替代传统体硅MOSFET最有效的器件。 然而, 针对FinFET的功耗分析在现阶段仍然缺失。 本文针对FinFET不同的电路结构特点, 采用PTM 32nm FinFETs模型在HSpice上进行了详尽的功耗来源与影响因素分析: 针对电路连接模式、背栅电压、输入信号歪斜、输出电容负载、电路输入状态、以前的状态、时序动作、温度等一些可能对功耗造成影响的因素进行了一一探讨。 需要特别关注的是, 与体硅MOSFET相比, 双栅FinFET器件的阈值电压增加了一个背栅电压的控制量, 本文针对这一FinFET特点进行了着重探讨。 通过量化和比较所有的功耗影响因素, 改进了已有的功耗库模型。 本文对于低功耗设计人员与CAD软件设计人员具有指导和借鉴意义。

A CORDIC Demodulator Platform for Digital-IF Receiver

In this paper, a novel device/circuit co-design scheme, namely Dynamic-Adjusting Threshold-Voltage Scheme (DATS) for independent-gate mode FinFET circuits has been proposed. The main idea of this scheme is that a pair of back-gate bias of FinFETs is adjusted dynamically to change threshold voltage according to the system operating frequency and operating mode, which could optimize circuit power, especially leakage power. The experimental and simulation result shows that the leakage power dissipation reduced greatly when circuits operate at the lower frequency, and the energy-delay product of FinFET circuits is reduced by 30% approximately.

Design of D flip-flops with low power-delay product based on FinFET

A 2-level FSK digital demodulator with CORDIC algorithm for digital-IF receiver is presented. The 2-level FSK noncoherent detector is designed based on counting the zero crossing points using new noise elimination technique. Synchronization control information is extracted from the amplitude signal through setting protection parameters. The output BER is 0.01% for input SNR of 1 dB with frequency offset 0.1 MHz. The digital-IF receiver including demodulator is implemented based on Xilinx Virtex-II XC2V3000-6FG676 FPGA.

Research on circuit level countermeasures for Differential Power Analysis attacks

A reconfigurable CORDIC demodulator platform and design method for digital-IF receiver is presented. A 2-level FSK demodulator for family network is implemented and tested on that platform with Xilinx VirtexII XC2V1000-4FG256 FPGA. The 2-level FSK noncoherent detector is designed based on counting the zero crossing points using new noise elimination technique. Synchronization control information is extracted from the amplitude signal through setting protection parameters. The output BER is 0.01% for input SNR of 1dB with frequency offset of 0.1MHz

High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2 m )

In this paper, FinFET has been introduced to the design of high performance D flip-flops. Based on the excellent electrical properties of FinFET, the SG-mode D flip-flop modified from original PHLFF by substituting SG-mode FinFET for planar MOSFET has a tremendous reduction of 87.0% on power-delay product (PDP). Considering the unique merits of multiple operating modes of FinFET, further optimization based on SG-mode PHLFF has been proposed to achieve lower PDP and more efficient area utilization rate. The simulation results indicate that the multi-mode PHLFF reduces the PDP by 92.6% and slightly decreases the number of transistors.