Chunlei Wu

A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration

In this paper, a novel junction depleted-modulation design to achieve equivalently abrupt tunnel junction of Si Tunnel FET (TFET) is proposed. By changing the gate layout configuration, the new Junction-modulated TFET can reliably and effectively achieve much steeper switching behavior and higher ON current without area penalty and special fabrication compared with traditional TFET. Further junction optimization by introducing the self-depleted doping pocket with much relaxed process requirements is also experimentally demonstrated based on the bulk Si substrate. With traditional Si CMOS-compatible process, the fabricated device shows a minimum substhreshold slope of 36mV/dec within one decade of drain current.

An Analytical Surface Potential Model Accounting for the Dual-Modulation Effects in Tunnel FETs

In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified. The dual-modulation effects in TFETs that the surface potential of the channel is alternatively controlled by the gate bias and drain bias in different operating regimes are emphasized and studied. The transition point corresponding to the switching between the two operating regimes is also analyzed quantitatively. For the first time, a closed-form analytical model of the surface potential in TFETs, including the impacts of both the gate voltage and drain voltage is proposed. Furthermore, a compact current model of the TFET-based on the derived surface potential expression is given. The model predicted tunneling current agree well with the TCAD simulation results in all operating regions of TFETs, which will be helpful for the circuit properties simulation of the TFET.

Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective

In this paper, a novel TFET design, called Pocket-mSTFET (PMS-TFET), is proposed and experimentally demonstrated by evaluating the performance from device metrics to circuit implementation for low-power SoC applications. For the first time, from circuit design perspective, TFETs performance in terms of ION, IOFF, subthreshold slope (SS), output behavior, capacitance, delay, noise and gain are experimentally benchmarked and also compared with MOSFET. By gate and source engineering without area penalty, the compatibly-fabricated PMS-TFET on SOI substrate shows superior performance with the minimum SS of 29mV/dec at 300K, high ION (~20μA/μm) and large ION/IOFF ratio (~108) at 0.6V. Largely alleviated super-linear onset issue, reduced Miller capacitance and delay, and much lower noise level were also experimentally obtained, as well as high effective gain. Circuit-level implementation based on PMS-TFET also shows significant improvement on energy efficiency and power reduction at VDD of 0.4V, which indicates great potential of this TFET design for low-power digital and analog applications.

Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling

In this paper, a closed-form current model for bulk tunneling field-effect transistor (TFET) is put forward. Based on the operation mechanism, the channel surface potential ϕsf which involves the impact of both the gate and the drain voltages is established for the first time. In addition, a new calculation method for the dynamic tunneling width, which is the critical parameter for the TFET modeling, is derived from the surface potential. The surface-potential-based current model is established which is in a good agreement with TCAD simulation results.摘要本文提出了一个针对隧穿场晶体管(TFET)的电流模型。 首先, 本文首次建立了包含栅压和漏压对隧穿过程共同影响的沟道表面电势的解析表达式; 其次, 本文提出了隧穿宽度的计算方法; 最后, 本文提出的电流模型与TCAD仿真结果有着良好的吻合并可用于SPICE电路仿真。

Design Guideline for Complementary Heterostructure Tunnel FETs With Steep Slope and Improved Output Behavior

In this letter, design guideline for complementary heterostructure tunnel FETs (C-HTFETs) is proposed based on the insight into the tradeoff between n-type and p-type HTFETs optimization. For the first time, the contradiction of source/channel material selection between n-type and p-type HTFETs is addressed, indicating that HTFETs integrated on the same materials system cannot achieve optimized n-type and p-type devices simultaneously. Optimized complementary III-V HTFETs based on two different source/channel materials systems are studied as design examples for further validation of the proposed design guideline, exhibiting both steep sub-threshold swing and improved output behavior in the n-type and p-type HTFETs. The conclusions are helpful to the prospective C-HTFETs design for low-power complementary logic applications.

First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

We have first manufactured Complementary Tunnel-FETs (C-TFETs) in standard 12-inch CMOS foundry. With abrupt tunnel junction consideration for improved TFET performance, technology of monolithically integrating C-TFET with CMOS is developed. Planar Si C-TFET inverter is also demonstrated, indicating a new electrical isolation requirement between neighboring devices for practical C-TFET integration on bulk substrate. For high-volume production, the variability of C-TFETs are experimentally investigated, demonstrating an intrinsic trade-off between performance enhancement and variability suppression induced by dominant variation source in traditional TFETs, which is mainly impacted by the band-to-band tunneling generation area. By new TFET device design, improved performance and variability simultaneously are experimentally achieved, and circuit-level implementation shows significant operation speed enhancement (up to 93%) and energy reduction (by 66%) at VDD of 0.4V, as well as remarkably suppressed variation, indicating its great potential for ultralow-power applications.

Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering

The low frequency noise (LFN) mechanisms of TFETs with different source junction design are experimentally studied for the first time, including the random telegraph signal (RTS) noise. Different from MOSFET, due to the non-local band-to-band tunneling (BTBT) mechanism and small LFN-generating area, both 1/f and 1/f2 LFN dependence can be observed in large TFETs with large device to device variability, as well as high noise. It is found that the “active” traps responsible for the noise mechanism are located in the area where electron-hole pairs generated by non-local BTBT, and the trap located at the maximum junction electric field tends to have relatively weak impacts on the TFET noise. With new abrupt tunnel junction design, it is observed that the device variability can be effectively alleviated with much lower noise level. In addition, a single-trap-induced RTS noise in TFETs with different source junction design is also experimentally investigated. New features, including strong VD dependence of RTS parameters and significantly high amplitude (~28%), indicate the desirable requirement for the source junction optimization in TFETs.

A Novel Tunnel FET Design With Stacked Source Configuration for Average Subthreshold Swing Reduction

In this paper, a novel heterostacked tunnel FET (HS-TFET) is proposed for steeper average subthreshold swing (SS). Different from conventional TFETs, HS-TFETs owns a stacked source configuration consisting of an upper source layer with a relatively larger bandgap material and an underlying source layer with smaller bandgap materials. Since smaller bandgap materials exhibit much higher band-to-band tunneling efficiency, the underlying layer of HS-TFET could provide extra drain current increment with increasing gate voltage, and thus effectively improve the subthreshold characteristics for steeper average SS. The simulation results show that the proposed Si-Ge-based HS-TFET can achieve much steeper average SS (25 mV/decade) than conventional Si TFET (42 mV/decade), exhibiting more than one decade higher I60 without leakage current degradation.

High performance tunnel field-effect transistor by gate and source engineering

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I(ON)/I(OFF) ratio (∼ 10(7)) at V(DS) = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ∼ 10(8) and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec(-1) was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

A closed-form capacitance model for tunnel FETs with explicit surface potential solutions

In this paper, a closed-form physical capacitance model for bulk tunnel FETs (TFETs) is proposed based on the surface potential approach for the first time. Fundamentally different from that in the MOSFET, the channel surface potential φsf in the TFET is alternately controlled by the drain bias and gate bias in different operation regions. On the basis of physical insight into the operation mechanism, the analytical model of φsf as a function of terminal bias is established. The Gaussian box is introduced to predict the surface potential profile near the source-body junction. Furthermore, the surface-potential-based capacitance model is derived and the calculated terminal capacitances show good agreement with the TCAD simulation results. With the essential physics considered, excellent validity of the model is achieved for bulk TFETs with a large range of structure parameters and SOI/double-gate (DG) TFETs.