Lingyi Guo

Comprehensive performance re-assessment of TFETs with a novel design by gate and source engineering from device/circuit perspective

In this paper, a novel TFET design, called Pocket-mSTFET (PMS-TFET), is proposed and experimentally demonstrated by evaluating the performance from device metrics to circuit implementation for low-power SoC applications. For the first time, from circuit design perspective, TFETs performance in terms of ION, IOFF, subthreshold slope (SS), output behavior, capacitance, delay, noise and gain are experimentally benchmarked and also compared with MOSFET. By gate and source engineering without area penalty, the compatibly-fabricated PMS-TFET on SOI substrate shows superior performance with the minimum SS of 29mV/dec at 300K, high ION (~20μA/μm) and large ION/IOFF ratio (~108) at 0.6V. Largely alleviated super-linear onset issue, reduced Miller capacitance and delay, and much lower noise level were also experimentally obtained, as well as high effective gain. Circuit-level implementation based on PMS-TFET also shows significant improvement on energy efficiency and power reduction at VDD of 0.4V, which indicates great potential of this TFET design for low-power digital and analog applications.

First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

We have first manufactured Complementary Tunnel-FETs (C-TFETs) in standard 12-inch CMOS foundry. With abrupt tunnel junction consideration for improved TFET performance, technology of monolithically integrating C-TFET with CMOS is developed. Planar Si C-TFET inverter is also demonstrated, indicating a new electrical isolation requirement between neighboring devices for practical C-TFET integration on bulk substrate. For high-volume production, the variability of C-TFETs are experimentally investigated, demonstrating an intrinsic trade-off between performance enhancement and variability suppression induced by dominant variation source in traditional TFETs, which is mainly impacted by the band-to-band tunneling generation area. By new TFET device design, improved performance and variability simultaneously are experimentally achieved, and circuit-level implementation shows significant operation speed enhancement (up to 93%) and energy reduction (by 66%) at VDD of 0.4V, as well as remarkably suppressed variation, indicating its great potential for ultralow-power applications.

Benchmarking TFET from a circuit level perspective: Applications and guideline

Low power applications have led to a boom in researches on new circuits based on steep-slope transistors, of which the objective is to overcome MOSFETs drawback of inevitable increasing leakage power while maintaining acceptable performance in low voltage operation. Among those emerging transistors, Tunnel FET (TFET) becomes a most promising one due to its low off current and compatibility with CMOS process. In order to guide the application and the improvement of TFET, in this paper from a circuit-level perspective, utilizing a newly defined benchmarking method, we figured out the frequency-VDD range in which Si TFET circuits show low power advantage over their MOSFET counterparts based on HSPICE simulations using calibrated compact model. A systematic and quantitative analysis was then conducted to further enlarge the application scope of TFET circuits, with a Figure of Merit (FOM) and a guideline for future TFET proposed.

New Understanding of Random Telegraph Noise Amplitude in Tunnel FETs

As one of the important sources of low-frequency noise, random telegraph noise (RTN) in tunnel FET (TFET) has attracted growing attention recently. However, there is still lack of explanation for the high-amplitude RTN, which may cause serious variability and reliability problems to TFET-based ultralow-power circuits. In this paper, we experimentally investigate the RTN amplitude characteristics in TFETs, revealing the mechanism of high-amplitude RTN. It is found that the nonuniform distribution of band-to-band tunneling (BTBT) generation rate along device width direction is responsible for the high-amplitude RTN. Locations with relatively higher BTBT generation rate may act as critical paths dominating the device current. “Lucky” trap located at a critical path can induce the high-amplitude RTN. With device width shrinking, the number of critical paths may be reduced, resulting in much higher maximum RTN amplitude. In addition, the impacts of process parameters on RTN amplitude are discussed. Both higher source doping concentration (

Multi-finger Schottky-Barrier tunneling FET with hybrid operation mechanism for steep transition and high on current

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Comprehensive investigation and design of Tunnel FET-based SRAM

and higher thermal budget can effectively mitigate the nonuniformity of BTBT generation rate along device width direction, causing suppressed RTN amplitudes. Considering that the higher thermal budget may lead to degraded device performance, the annealing process should compromisingly be designed in terms of both variation and device performance.

Benchmarking of multi-finger Schottky-Barrier tunnel FET for ultra-low power applications

This paper discusses a kind of novel steep-slope switch device, named as multi-finger Schottky-Barrier TFET (MFSB-TFET), with hybrid adaptive operation mechanism, for higher on current, steeper slope as well as low off current. With the on state dominated by Schottky injection current, transition region dominated by band-to-band tunneling and the off current greatly suppressed with increased effective barrier height, the proposed silicon-based MFSB-TFET has experimentally demonstrated low SS, high on current and high on-off current ratio, exhibiting great potentials for ultra-low-power circuit applications.

New Insights Into Energy Efficiency of Tunnel FET With Awareness of Source Doping Gradient Variation

In this work, the impacts of electrical characteristics of Tunnel FET (TFET) on the SRAM design are systemically investigated for the first time from the perspective of memory array. A novel 10T TFET SRAM design is also proposed to overcome the challenges and improve the circuit stability. By using a calibrated compact model, the simulated static power of 10T TFET SRAM can be much lower than traditional 6T MOSFET SRAM, especially at the low supply voltage of 0.5V. In addition, the cells stability is also largely improved with the largest noise margin compared with reported 7T TFET SRAM design and traditional 6T MOSFET SRAM.