Rundong Jia

Ion Gated Synaptic Transistors Based on 2D van der Waals Crystals with Tunable Diffusive Dynamics

Neuromorphic computing represents an innovative technology that can perform intelligent and energy-efficient computation, whereas construction of neuromorphic systems requires biorealistic synaptic elements with rich dynamics that can be tuned based on a robust mechanism. Here, an ionic-gating-modulated synaptic transistor based on layered crystals of transitional metal dichalcogenides and phosphorus trichalcogenides is demonstrated, which produce a diversity of short-term and long-term plasticity including excitatory postsynaptic current, paired pulse facilitation, spiking-rate-dependent plasticity, dynamic filtering, etc., with remarkable linearity and ultralow energy consumption of ≈30 fJ per spike. Detailed transmission electron microscopy characterization and ab initio calculation reveal two-stage ionic gating effects, namely, surface adsorption and internal intercalation in the channel medium, causing different poststimulation diffusive dynamics and thus accounting for the observed short-term and long-term plasticity, respectively. The synaptic activity can therefore be effectively manipulated by tailoring the ionic gating and consequent diffusion dynamics with varied thickness and structure of the van der Waals material as well as the number, duration, rate, and polarity of gate stimulations, making the present synaptic transistors intriguing candidates for low-power neuromorphic systems.

First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

We have first manufactured Complementary Tunnel-FETs (C-TFETs) in standard 12-inch CMOS foundry. With abrupt tunnel junction consideration for improved TFET performance, technology of monolithically integrating C-TFET with CMOS is developed. Planar Si C-TFET inverter is also demonstrated, indicating a new electrical isolation requirement between neighboring devices for practical C-TFET integration on bulk substrate. For high-volume production, the variability of C-TFETs are experimentally investigated, demonstrating an intrinsic trade-off between performance enhancement and variability suppression induced by dominant variation source in traditional TFETs, which is mainly impacted by the band-to-band tunneling generation area. By new TFET device design, improved performance and variability simultaneously are experimentally achieved, and circuit-level implementation shows significant operation speed enhancement (up to 93%) and energy reduction (by 66%) at VDD of 0.4V, as well as remarkably suppressed variation, indicating its great potential for ultralow-power applications.

Deep insights into dielectric breakdown in tunnel FETs with awareness of reliability and performance co-optimization

The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of dielectric in TFET also leads to the different mechanisms between soft breakdown and hard breakdown failure. Moreover, dielectric-field-associated parameters are discussed in detail, showing an intrinsic trade-off between dielectrics reliability and device performance optimization caused by the positive correlation between dielectric field and source junction field. A new robust design consideration is further proposed for reliability and performance co-optimization, which is experimentally realized by a new TFET design with both dramatically improved performance and reliability, indicating its great potentials for ultralow-power applications.

A novel deep-impurity-level assisted tunneling technology for enhanced interband tunneling probability

In this work, a novel deep-impurity-level assisted tunneling technology with enhanced band to band tunneling (BTBT) probability is proposed and experimentally demonstrated. Through implanting deep level impurities in the tunnel junction, continuous deep level states can be introduced to facilitate the BTBT process for significant BTBT probability boosting. Compared with conventional tunnel diodes, the fabricated deep-impurity-level assisted tunnel diodes exhibit 7.8× and 23× current enhancement in P++/N+ and N++/P+ tunnel diodes respectively, showing its great potential for future current enhancement in tunnel FETs.