Kai-Wen Yao

Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0.18-

This paper presents the design and experimental evaluation of a new type of irreversible energy recovery logic (ERL) families called complementary energy path adiabatic logic (CEPAL). It inherits the advantages of quasi-static ERL (QSERL) family, but is with improved driving ability and circuit robustness. The proposed logic style features no hold phase compared to its QSERL counterpart under the same operation conditions; thereupon no feedback keeper is required so that considerable improvements in area and power overheads can be achieved. Moreover, its throughput becomes twice as high as that of QSERL when their frequencies of power clocks (PCs) are identical. Results on the impact of variation on CEPAL are provided. Comparison between CEPAL and other known low-power logic style achieving iso-performance, namely, subthreshold logic is also given. In order to demonstrate workability of the newly developed circuit, an 8-bit shift register, designed in the proposed techniques, has been fabricated in a TSMC 0.18-mum CMOS process. Both simulation and measurement results verify the functionality of such a logic, making it suitable for implementing energy-aware and performance-efficient very-large scale integration (VLSI) circuitry.

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In the fields of wireless bioelectronics implants and sensor network systems, amplitude shift keying (ASK) is one of the most commonly used schemes employed to modulate the baseband signal with reference to the intermediate or even the carrier frequency. In this study, a demodulator architecture capable of dealing with most of the previous limitations in an ASK-utilized medical implant, especially in want of being powered through wireless delivering, is proposed. It features the abilities of working on a very small modulation index and being provided without any R/C component(s) inside by means of a self-sampling scheme. The design has been implemented in an 18-mum CMOS process. The demodulator circuit occupies a die size of merely 32.3 times 14.5 mu m2. Analytic results from both simulated gradation and fabricated chips show that the proposed circuit can operate at a carrier of 2 MHz and achieve a modulation rate of up to 50%. The results also demonstrate that the presented work can still perform a proper demodulation even with a modulation index beneath 5.5%. An average power of approximately 336 muW was confirmed in return for the remarkable advantages. All aspects regarding the design, including a review of the prior arts, system consideration, circuit description, and analyses from simulation phase to actual measurement, are presented in detail.

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This paper describes a low-noise and low-power architecture of the differential difference amplifier (DDA) for neural recording system. The proposed neural amplifier combines DC offset rejection and low-frequency cutoff tuning without off-chip components. DC offset rejection is carried out by ac coupling which is realized by series connection of a capacitor and a MOS-bipolar pseudoresistor. Low-frequency cutoff tuning permits recording local field potential or neural action potential. Frequency tuning mechanism depends on the feedback capacitor and floating tunable resistor which constructs a low frequency pole nearby 100 Hz. The proposed design is in TSMC 0.18 mum 1P6M CMOS process, which achieves gain of 40.8 dB, passband from 107 Hz to 10.3 kHz, input-referred noise of 4.83 muVrms, power consumption of 25.9 muW, and 0.084 mm2 of chip area.

A Truly Low-Cost High-Efficiency ASK Demodulator Based on Self-Sampling Scheme for Bioimplantable Applications

This paper describes a bioamplifier that employs a voltage-controlled-pseudo-resistor to achieve tunable bandwidth and wide operating voltage range for biomedical applications. The versatile pseudo-resistor employed provides ultra-high resistance for ac coupling to cancel the dc offset from electrode-tissue interface. The voltage-controlled-pseudo-resistor consists of serial-connected PMOS transistors working at the subthreshold region and an auto-tuning circuit that makes sure the constant (time-invariant) control-voltage of the pseudo-resistor. This bandwidth-tunable bioamplifier is designed in a 0.18-µm standard CMOS process, achieving a gain of 40.2dB with 10.35-µW power consumption. The designed chip was also used to develop the proof-of-concept prototype. An operation bandwidth of 9.5kHz, input-referred noise of 5.2 µ V rms from 6.3Hz to 9.5kHz and 5.54 µ V rms from 250Hz to 9.5kHz, and a tunable cutoff-frequency from 6.3-600Hz were demonstrated to prove our design.

A differential difference amplifier for neural recording system with tunable low-frequency cutoff

SUMMARY We developed an inductively powered integrated electronic prosthesis, allowing for the trade-offs among implant functionality, circuit complexity, power consumption, hardware cost, and integrity of data recovery, for a multichannel microstimulation circuitry. The proposed prosthesis features energy efficiency and is capable of up to 40 scan/s with 240 stimulus channels in mode I and three times resolution at the same scan rate in mode II under a carrier frequency of 2 MHz. In order to satisfy future upgrade demands, the prototype has been constructed with a 16-channel-based stimulation scheme so that the spatial resolution of the design can be extended toward various experimental purposes. The circuit techniques used in the system are detailed. Results from fabricated chips using a 0.18-µm CMOS process are given as proof of concept. Copyright

A bandwidth-tunable bioamplifier with voltage-controlled symmetric pseudo-resistors

A fully integrated CMOS rectifier, intended for inductively powered electronic implants and featuring ultra-low-loss characteristic, is presented. By making use of high-performance active diodes fulfilling almost ideal switching (zero forward voltage drop) and circuit to be provided with negative resistance, the proposed design is able to achieve an maximum conversion efficiency of more than 90% when designed in a 0.18-mum standard CMOS process, without any special device requiring additional manufacturing procedures. As a result, the proposed design dramatically reduces the production cost. Estimations in all aspects regarding the performance of the rectifier are given in this paper.

A CMOS multichannel electrical stimulation prototype system

A complementary energy path adiabatic logic (CEPAL) designed for ubiquitous large-scaled digital systems achieves higher noise immunity, higher driving ability, and reduced power density than the prior quasi-static structure. By applying CEPAL to the clocked storage elements (i.e. DFFs) with a diode-shared scheme, the overall efficiency is dramatically improved without increasing the design overhead compared with the quasi-static implementation. A test module consists of an 8-bit CEPAL shift register (SFR) has been laid out in a 0.18-μm CMOS process. Post-layout analytic results, including parasitic effect and exhibiting the benefits of various aspects in the proposed fashion, are given as proof of concept.

Efficient CMOS rectifier for inductively power-harvested implants

Stimulator is a key for implantable applications such as neural prostheses, which provides injected current flowing directly to the neural interfacing and cells or tissues of interest to activate neural responses as long as the electric charge thresholds involved can be achieved. This papers aims presenting a preliminary research results toward an efficient stimulator for which particular emphasis is put on the efficiency point of view. Analysis and design are introduced. Experimental results from our first-edition proof of concept are given.

Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applications

This paper reports on the results of an integrated rectifier for wirelessly powered medical electronic devices. To considerably enhance the rectification efficiency, high-performance active diodes are incorporated. In addition, a fine cost-effective and energy-efficient back telemetry mechanism with increased robustness against physical variations in the external reader and internal transponder (implant) has been equipped. Fabricated in a 0.18-μm technology, the design demonstrates that it is able to achieve maximum conversion efficiency approximately 90%, while at the same time dramatically reducing the overhead to practical implementation. It has also been proved for its full functionality in the asserted built-in robust back telemetry.

On investigation into A CMOS-process-based high-voltage driver applied to implantable microsystem

A chopper stabilized front-end with an active dc-suppressed topology used to record extracellular neural action potentials and local field potentials is presented in this paper. An active dc-suppressed topology, such as a bandpass filter, containing an amplifier with an integrator on the feedback path, suppresses baseline drift and assures weak inversion operations of input stages of the proposed bandpass filter. Floating tunable resistors are also employed to produce large resistance, providing large time constant to reduce low frequency noise. The proposed front-end circuitry needs no external capacitors and resistors and adjusts highpass cutoff frequency arbitrarily by altering control voltage of floating tunable resistors. The work in this paper, designed in a 0.18-µm CMOS process, provides sufficiently high linearity at least 10-bit SNDR, a midband gain of 63 dB, and signal bandwidth of approximately 13 kHz. Supplied at 1.8 V, the proposed front-end consumes around 231 µW. With the proposed chopping technique, a total of 7.05-µVrms input-referred noise can be achieved at the signal bandwidth.