Lei L. Mercado

Impact of flip-chip packaging on copper/low-k structures

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.

Failure mechanism study of anisotropic conductive film (ACF) packages

Anisotropic conductive film (ACF) consists of an adhesive polymer matrix with dispersed conductive particles. In flip-chip technology, ACF has been used in place of solder and underfill for chip attachment to glass or organic substrates. The filler particles establish the electrical contacts between the interconnecting areas. ACF flip-chip bonding provides finer pitch, higher package density, reduced package size and improved lead-free compatibility. Nevertheless, the interconnection is different from traditional solder joints, the integrity and durability of the ACF interconnects have major concerns. Failures in anisotropic conductive film (ACF) parts have been reported after temperature cycling, moisture preconditioning and autoclave. The failures have not been well understood and have been attributed to a wide variety of causes. This paper investigates the failure mechanism of ACF using finite element simulation. From a failure-initiation point of view, the response of ACF packages to environmental (temperature and humidity) exposure is very different from standard underfilled packages. These differences cause the ACF package to fail in different ways from an underfilled package. Simulation results have shown that moisture-induced ACF swelling and delamination is the major cause of ACF failure. With moisture absorption, the loading condition at the interface is tensile-dominant, which corresponds to lower interface toughness (or fracture resistance). This condition is more prone to interface delamination. Therefore, the reliability of ACF packages is highly dependent on the ACF materials. The paper suggests a new approach toward material selection for reliable ACF packages. This approach has very good correlation with experimental results and reliability testing of various ACF materials.

Analysis of flip-chip packaging challenges on copper low-k interconnects

As industry trends drive increased integration and speed, Cuilow-k structures are the desired choice for advanced IC circuits. A simulation methodology has been developed to study the flip-chip packaging effect on the Cullow-k structures. Multi-level submodeling techniques have heen used to bridge the scale difference between the flip-chip packages and the metalidielectric stacks. Interface fracture mechanics-based approach is used to determine the crack driving force at each interface. The impact of the die-attach process on interconnect reliability has been evaluated. To achieve smaller feature size and higher speed in future chips, we can replace Si02 with low-k dielectric material in all via and trench layers, or increase the number of metal layers. This paper evaluates the effect of placing low-k as last metal dielectric and low-k at all via and trench layers, as well as the effect of eight-layer metal/dielectric stack compared with the four-layer metal stack. The future flip-chip Cuilow-k packages are facing higher possibilities of adhesive or cohesive failure near the low-k interface. This paper provided a quantitative evaluation of the increased risk, thus providing guidelines to the next level of low-k flipchip packages.

Mechanics-based solutions to RF MEMS switch stiction problem

RF micro-electro-mechanical systems (MEMS) switches are an attractive solution to switch antenna bands and transmit/receive switching for future multiband, high bandwidth cell phones. However, Stiction is a major concern for resistive switches with metal-to-metal contact. An iterative-coupled electrostatic-structural analysis is utilized to evaluate the effect of design parameters on restoring force of MEMS switches. Parameters including metal thickness, dielectric thickness, beam-to-ground gap height, metal and dielectric width, and cantilever beam length can be evaluated. The electrostatic force is first calculated based on the electrical field component. A structural analysis is then performed to determine the cantilever beam deflection due to the electrostatic force. A unique integrated empirical-numerical method is used to quantitatively determine the stiction force based on measured actuation voltages for real devices. The analysis can provide quick evaluation and screenings of proposed designs to determine if their actuation voltage falls in the acceptable range. Simulation prediction agrees very well with test measurements. Although increasing cantilever thickness and shortening cantilever length both increase restoring force, the actuation voltage will increase significantly as a result. The most favorable modification is to increase the electrode area. A short and wide structure with a large area can increase restoring force while maintaining low actuation voltage. Compared to similar bi-layer designs, sandwich designs can be actuated at further reduced voltages without changing the beam restoring force. In addition, the sandwich structure, being thermal-stress-balanced, is less sensitive to temperature excursion. With the properly selected design parameters, the new designs will be able to achieve the break away restoring force of the original design at much lower actuation voltages. Switches with good electrical as well as mechanical performances have been successfully fabricated.

Evaluation of die edge cracking in flip-chip PBGA packages

Increasing die size and large coefficient of thermal expansion (CTE) mismatch in flip-chip plastic ball grid array (FC-PBGA) packages have made die fracture a major failure mode during reliability testing. Most die fracture observed before was die backside vertical cracking, which was caused by excessive package bending and backside defects. However, due to die edge defects induced by the singulation process and the choice of underfill material, an increasing number of die cracks were found to initiate from die edge and propagate horizontally across the die. In order to improve package reliability and performance, die edge cracking has to be eliminated. An extensive finite element analysis was completed to investigate die edge cracking and find its solutions. A fracture mechanics approach was used to evaluate the effect of various package parameters on die edge initiated fracture. Strain energy release rate was found to be an effective technique for evaluating die edge initiated fracture from singulation-induced flaws. The impact of initial flaw size and a variety of package parameters was investigated. Unlike in die backside cracking, the dominant parameters causing die edge horizontal fracture are more closely related to local effects.

A simulation method for predicting packaging mechanical reliability with low /spl kappa/ dielectrics

It is essential to understand the impact of packaging on chips with copper/low k structures. In this paper, a multi-level, multi-scale modeling technique is used to study the die attach process. Four-level models are built to analyze the packaging impact on the wafer-level behavior. An interface fracture mechanics-based approach is adopted to predict interface delamination. The impact of thin film residual stresses is studied at both the wafer level and package level. Both Plastic Ball Grid Array (PBGA) and Ceramic Ball Grid Array (CBGA) packages are evaluated. Critical failure locations and interfaces are identified for both packages. Two solutions are suggested to prevent catastrophic delamination in copper low-k flip-chip packages.

Use-condition-based cyclic bend test development for handheld components

For handheld electronic applications such as cell phones and personal digital assistants (PDAs), repeated key strokes could result in considerable flexure of the printed circuit board (PCB) mounted inside the housing. In this study, a standardized four-point bend test, including test board design, test setup, and test input level, has been developed. The S-N curve has been obtained by plotting the reliability at all deflection levels as a function of solder joint strain energy density. The effect of test frequency has also been evaluated. The reliability model prediction of three-point bend reliability matches the experimental data extremely well. The transfer function between reliability stressing and field condition is a strain-energy-density-based power law relationship. Finite element simulation has been conducted for the worst-case cell phone subjected to key presses. The use condition data including strain profiles and frequency have been incorporated in the field life prediction. The four-point bend performance can be converted into the component reliability during cell-phone field use conditions. This study establishes the correlation between the use conditions and reliability tests. The cyclic four-point bend test will be implemented in the JEDEC bend test standard for handheld components.

Impact of solder pad size on solder joint reliability in flip chip PBGA packages

A variety of package parameters impact package reliability. One of the parameters that does not get much attention is the variations in package design that are assembly and vendor related. It was shown in this study that the solder pad size plays a big role in solder joint reliability. The difference in solder pad size due to different vendors and processes can affect the reliability considerably. In certain cases, the pad size effect can be so significant that it will override the effect of substrate thickness. Our work indicates that in order to obtain good correlations between predictive engineering results and reliability tests data, this factor should not be ignored. In this paper, finite element analysis was used to study the impact of substrate thickness on solder reliability for flip-chip PBGA (plastic ball grid array) packages. The simulation results were experimentally validated with moire interferometry. Both numerical and experimental results indicated that better solder reliability could be achieved by using thicker substrate. However, the size of BGA solder pad was found to be crucial to BGA life. In order to achieve higher C5 (controlled collapse chip carrier connection) reliability, a larger solder pad is preferred.

Multichip package delamination and die fracture analysis

Multichip mechatronic power packages have been developed in Motorola for automotive applications. Copper heat sink based metal substrates were used to improve thermal and electrical performance. In the early stage of development, mold delamination and die cracking have been observed after assembly. With some mold compound materials, die backside have large delaminated areas, while with other mold compound, delamination stops early but die cracks. Finite element analysis, incorporated with interface fracture mechanics method, has been conducted to understand these phenomena. Impact of mold material properties and package geometry on post-assembly delamination has been evaluated. Good agreements have been obtained between experimental data and the simulation results. The phenomenon of crack branching into the die was also studied. Finite element simulation can be used to predict whether and when the crack at the interface will turn and crack the die. With a thorough understanding of the failure mechanism, both mold delamination and die cracks have been eliminated in the final package development.

Analysis of RF MEMS switch packaging Process for yield improvement

Radio frequency microelectro-mechanical systems (RF MEMS) switches offer significant performance advantages in high-frequency RF applications. The switches are actuated by electrostatic force when voltage was applied to the electrodes. Such devices provide high isolation when open and low contact resistance when closed. However, during the packaging process, there are various possible failure modes that may affect the switch yield and performance. The RF MEMS switches were first placed in a package and went through lid seal at 320degC. The assembled packages were then attached to a printed circuit board at 220degC. During the process, some switches failed due to electrical shorting. Interestingly, more failures were observed at the lower temperature of 220degC rather than 320degC. The failure mode was associated with the shorting bar and the cantilever design. Finite element simulations and simplified analytical solutions were used to understand the mechanics driving the behaviors. Simulation results have shown excellent agreement with experimental observations and measurements. Various solutions in package configurations were explored to overcome the hurdles in MEMS packaging and achieve better yield and performance