Clark C. Guest

Comparison between optical and electrical interconnects based on power and speed considerations.

Conditions are determined for which optical interconnects can transmit information at a higher data rate and consume lc3s power than the equivalent electrical interconnections. The analysis is performed for free-space optical intrachip communication links. Effects of scaling circuit dimensions, presence of signal fan-out, and the use of light modulators as optical signal transmitters are also discussed.

Iterative encoding of high-efficiency holograms for generation of spot arrays

An iterative discrete on-axis encoding method for computer-generated holograms (termed IDO encoding) has been developed. The binary IDO method employs simulated annealing to optimize the hologram phase delay and reduce sensitivity to fabrication tolerances. Computer-simulation results indicate that binary phase IDO encoding is capable of generating two-dimensional spot arrays with diffraction efficiencies larger than 70%. An experimentally fabricated hologram, designed to account for a 6% manufacturing hologram thickness tolerance, produced a 3 x 3 array of spots with 59% diffraction efficiency. The binary IDO algorithm can be employed to encode arbitrary images with twofold rotation symmetry.

Perceptual Temporal Quality Metric for Compressed Video

This paper presents a metric to quantify frame loss according to the impact on perceived temporal quality. This metric particularly aims at measuring the temporal quality degradation caused by both regular and irregular frame loss. Experimental results with subjective viewing demonstrate high performance on prediction of perceptual temporal quality.

Holographic Optical Interconnects For VLSI

This paper introduces new applications and design trade-offs anticipated for free-space optical interconnections of VLSI chips. New implementations of VLSI functions are described that use the capability of making optical inputs at any point on a chip and take advantage of greater flexibility in on-chip signal routing. These include n-port addressable memories, CPU clock phase distribution, hardware multipliers, and dynamic memory refresh, as well as enhanced testability. Fault tolerance and production yields may be improved by reprogramming the optical imaging system to circumvent defective elements. These attributes, as well as those related to performance alone, will affect the design methodology of future VLSI ICs. This paper focuses on identifying the design issues, their possible solutions, and their impact on VLSI design tech-niques and, finally, presents some preliminary measurements on various sys-tem components.

Optical digital logic operations by two-beam coupling in photorefractive material

The nonlinear phenomena of signal beam saturation, pump beam depletion, and optically controlled coupling coefficient of two-beam interaction in photorefractive materials are analyzed. Application of these phenomena to digital logic operations is discussed and supported by experimental results obtained in photorefractive BaTiO3.

Comparison between electrical and free space optical interconnects for fine grain processor arrays based on interconnect density capabilities

Optically interconnected processor arrays are compared to conventional fully electronic processor arrays in terms of interconnect density capabilities. A complexity model is introduced that allows the calculation of the array area growth rate as an asymptotic function of the number of processing elements in the array Lower bounds on the area growth rate of electrically interconnected processor arrays are compared to upper bounds for free-space optically interconnected circuits that employ computer generated holograms. Results indicate that for connection networks such as the hypercube, perfect shuffle and crossbar networks, that have a high minimum bisection width (a measure of the global nature of an interconnect topology) and contain some degree of spatial invariance, optically interconnected circuit area growth rates are below lower bounds on VLSI circuit growth rates.

Proteogenomic Database Construction Driven from Large Scale RNA-seq Data

The advent of inexpensive RNA-seq technologies and other deep sequencing technologies for RNA has the promise to radically improve genomic annotation, providing information on transcribed regions and splicing events in a variety of cellular conditions. Using MS-based proteogenomics, many of these events can be confirmed directly at the protein level. However, the integration of large amounts of redundant RNA-seq data and mass spectrometry data poses a challenging problem. Our paper addresses this by construction of a compact database that contains all useful information expressed in RNA-seq reads. Applying our method to cumulative C. elegans data reduced 496.2 GB of aligned RNA-seq SAM files to 410 MB of splice graph database written in FASTA format. This corresponds to 1000× compression of data size, without loss of sensitivity. We performed a proteogenomics study using the custom data set, using a completely automated pipeline, and identified a total of 4044 novel events, including 215 novel genes, 808 novel exons, 12 alternative splicings, 618 gene-boundary corrections, 245 exon-boundary changes, 938 frame shifts, 1166 reverse strands, and 42 translated UTRs. Our results highlight the usefulness of transcript + proteomic integration for improved genome annotations.

Modification of backpropagation networks for complex-valued signal processing in frequency domain

It is pointed out that existing backpropagation networks cannot be used for many signal-processing tasks because the signals are often represented with complex values. A complex-valued learning algorithm is derived for a backpropagation network where one or more of the inputs, outputs, and weight factors are complex-valued. The complex valued backpropagation network is tested with exclusive-OR problems for complex inputs, outputs, and weights. The network shows excellent mapping performance for this problem

Implementation of optical interconnections for VLSI

This paper reports on the progress in implementing optical interconnections for VLSI. Four areas are covered: 1) the holographic optical element (HOE), 2) the laser sources, 3) the detectors and associated circuits forming an optically addressed gate, and 4) interconnection experiments in which five gates are actuated from one source. A laser scanner system with a resolution of 12 µm × 20 µm has been utilized to generate the HOEs. Diffraction efficiency of the HOE and diffracted spot size have been measured. Stock lasers have been modified with a high-frequency package for interconnect experiments, and buried heterostructure fabrication techniques have been pursued. Measurements have been made on the fabricated photodetectors to determine dark current, responsivity and response time. The optical gates and the overall chip have been driven successfully with an input light beam, as well as with the optical signal interconnected through the one to five hologram.

Simulated annealing algorithm for binary phase only filters in pattern classification

A binary phase only filter is encoded with a simulated annealing algorithm to classify two similar characters in a variety of fonts. Characters that cannot be distinguished with conventional filter encoding methods are clearly distinguished with the optimized binary phase only filter using a simulated annealing algorithm. This method gives zero error classification rate for tested characters. Correlation performance of the optimized binary phase only filter is compared with the binary phase only filters encoded with conventional methods. The computational requirements for optimizing the filter are not excessive.