Claudius Feger

Evaluating polyimides as lightguide materials.

Lightguides were fabricated from three commercial polyimides of which one contains one and the others contain two hexafluoroisopropylidene (6F) groups. The latter are isomers using either the para or the meta isomer of the same diamine. As the number of 6F groups increases the optical losses of the corresponding lightguides decreases. In thick lightguides of the two 6F groups containing polyimides, loss values below 0.1 dB/cm can be realized using optimized conditions. Two mechanisms-ordering with or without charge transfer complex formation and voids or pinholes-are seen to be responsible for optical losses. The second type of losses can be reduced by cure optimization. Where ordering is possible annealing leads to increased optical losses. Geometrical restraint of the ordering, however, leads to loss reduction in otherwise identical conditions. Losses observed in the bulk are always higher than in the top and bottom layers of the polyimide films.

Ultraprecision machining of polymers

Abstract The single-point diamond machining of several polymeric materials has been investigated. The final surface structure and roughness of the workpiece is determined by well-established fundamentals of polymer mechanics. Material is removed via ductile, brittle, or transitional mechanisms that depend on polymer properties such as glass transition temperature, relaxation time, degree of crosslinking, and viscosity. For some materials, the mechanism could be changed from ductile to brittle with a change of operating and tool parameters. In brittle materials, the surface roughness is largely controlled by the rake face angle of the diamond. For ductile workpieces, the melt viscosity of the polymer is important. Crosslinked materials are restricted from ductile behavior by the presence of chemical bonds. As a result, material removal occurs by rupture or an extreme fracture process. With an understanding of polymer behavior, suitability of new materials for single-point diamond machining can be assessed. The change of successful processing within the operating range of the tool can be determined with a minimum number of trial and error experiments.

Ultrafine-pitch C2 flip chip interconnections with solder-capped Cu pillar bumps

PoP structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch of less than 80 µm or less, an ultra-fine-pitch flip chip interconnection technique is required. C4 flip chip technology is widely used in area array flip chip packages, but it is not suitable in the ultrafine-pitch flip chips because the C4 solder bumps melt and collapse on the wide opening Cu pads. Although the industry uses ultrafine-pitch interconnections between Au stud bumps on a chip and Sn/Ag pre-solder on a carrier, this flip chip technique has two major problems. One is that the need for bumps on both die and carrier drives up material costs. The other is that the long bonding process time required in the individual flip chip bonding process with associated heating and cooling steps demands large investments in equipment. To address these problems, we developed the mount and reflow with no-clean flux processes, and new interconnection techniques were developed with Cu pillars and Sn/Ag solder bumps on Al pads for wirebonding, were developed. It is very easy to control the gap between die and substrate by adjusting the Cu pillar height. Since it is unnecessary to control the collapse of the solder bumps, we call this the C2 process for direct Chip Connection (C2). The C2 bumps are connected to Cu substrate pads, which are a surface treated with OSP (Organic Solder Preservative), with reflow and no-clean processes. This technology creates the SMT/Flip Chip hybrid assembly for SoP (System on Package) use. We have produced 50 µm-pitch C2 interconnections and tested their reliability. The interconnection resistance increase caused by the reliability testing is quite small. It is clear that C2 flip chip technology provides robust solder connections at low cost. Also the C2 structure with a low-k device was evaluated and no failures were observed at 1,500 cycles in the thermal cycle test. This indicates that low-k C2 structures seem robust. For finer pitch flip chip interconnections, a wafer-level underfill process is needed to overcome the limitations of the standard capillary underfill process for ultra-narrow spaces. To date, a wafer- level underfill process exists for the C2 process with an 80-µm pitch. In addition to fine pitch interconnections, a die thickness of 70 µm is required to reduce the final stack height. Such thin die cannot be processed by the C2 process because such dies slip too easily during the reflow process. To resolve this issue, a Post-Encapsulation Grinding (PEG) method was developed. In this method the die is ground to less than 70 µm after joining and underfilling. This report presents the PEG method and reliability test results for die thicknesses 20 µm, 70 µm and 150 µm.

The over-bump applied resin wafer-level underfill process: Process, material and reliability

The over bump applied resin (OBAR) process is a wafer-level underfill (WLUF) process in which a filled resin is applied over the bumps of a wafer and, dried. The wafer is diced into coated chips which are aligned and joined to a substrate resulting in an underfilled flip chip package. This process has been evaluated by IBM on several test vehicles in close cooperation with Henkel (formerly Abelstik) who developed a material specifically to fit this process. The critical steps to make this technology work are alignment of OBAR coated chip to a substrate, elimination of significant voids, formation of a fillet with appropriate shape and size, fluxing and solder joining. The reliability of the material was evaluated after capping and BGA (Ball Grid Array) attach through JEDEC level 3 preconditioning followed by DTC (deep thermal cycling), T&H (temperature and humidity), and HTS (high temperature storage). While some improvements are still needed, the OBAR process has been shown to be a viable alternative to capillary underfill application.

Development of wafer level underfill materials and assembly processes for fine pitch Pb-free solder flip chip packaging

We developed a latent curing, low outgassing wafer level underfill (WLUF) material and applied fast temperature ramping to achieve 100% electrically and metallurgically good flip chip solder joints. Also, void formation within the underfill material during the bonding process was minimized. Subsequently, these voids were virtually eliminated during a post cure process of the WLUF material which uses pulsed amplitude pressure. A WLUF with 60% (weight) filler was applied by spin coating onto a wafer with Pb-free solder bumps. Following B-stage curing at 90°C, the thickness was measured to be 20 microns over the solder bump height. In the B-staged state, this WLUF is stable at room temperature for several weeks. After the wafer was diced into chips, a chip was aligned and joined to a substrate with an optimized heating and cooling cycle. This WLUF assembly process has been evaluated using a flip chip test vehicle with 150 micron pitch and 3,300 area array solder bumps. The chip bumps were SnAg solder and the pre-solder on the substrate was SnAgCu. The size of the test chip was 9 × 13 mm and the test substrate was 42.5 × 42.5 mm. The test chip and substrate were designed to allow both two and four wire contact resistance measurements of the electrical interconnect structures. We successfully demonstrated 100% electrically and metallurgically good Pb-free joints. Voids inside the WLUF after flip chip bonding were decreased significantly using the pulsed amplitude pressure, post cure process. Scanning acoustic microscopy (SAM) analysis showed nearly void-free underfill bonding. After JEDEC level three preconditioning, environmental stress testing was completed and included 1000 deep thermal cycles of −55 to 125°C; 1000 hrs at 85C/85% temperature and humidity; and 1000 hrs of 150°C high temperature storage. Contact resistance measurements were made at time zero, after preconditioning and every 250 cycles or hours of environmental stress. The contact resistance measurements were stable on all parts. Detailed material and process development, and reliability test results are described in this paper.

Wafer level underfill for area array Cu pillar flip chip packaging of ultra low-k chips on organic substrates

Wafer level underfill (WLUF), coated and B-staged on the wafer before dicing and flip chip bonding, protects and preserves interconnects and Back-End-of-Line (BEOL) structures by the presence of the underfill during the chip joining process. However, there are significant new challenges in formulating WLUF materials and developing the processes for area array flip chip packaging of silicon chips on organic substrates. The use of highly filled WLUF in conjunction with Ultra Low-k (ULK) chips which are larger than 10 × 10 mm and interconnected with Cu pillars to organic substrates has not yet been reported in the literature. It has been very challenging to achieve 100% electrically and metallurgically good Pb-free solder joints without WLUF voids. In this paper, details of flip chip packaging processes with highly filled WLUF materials (60 wt% fillers) will be presented including coating, dicing, bonding, and curing. The size of the test chip was 13×17mm and the test substrate was 42.5×42.5mm with over 8,000 area array interconnects. The chip bumps were 40 micron tall Cu pillars capped with 10 microns of SnAg solder (Ag >; 1.5 wt%) and the pre-solder on the substrate was SnAgCu (Ag >; 3.0 wt%). During the WLUF spin coating process, it is important to maintain uniform filler distribution as well as thickness uniformity. We achieved a tack-free surface after B-stage cure and the surface roughness was less than 0.2 micron. Since the wafer has ULK (k<;2.4) dielectric, the wafer requires laser grooving before the blade dicing to reduce the stress during wafer sawing. We introduced a new dicing method to apply laser grooving for WLUF flip chip packages. When WLUF is used for flip chip packaging of 13×17 mm size chips on organic substrates, the WLUF should be inherently fluxing to achieve metallurgically good solder joints by melting and solidification of the solder during the bonding process because larger size area array chip packages require higher reliability criteria than smaller size peripheral chip packages. However, the flux capability is a likely source of voids in the WLUF after bonding. These voids were eliminated during a post cure process of the WLUF material by using hydrostatic pressure. In addition, fillers in the 60 wt% loaded WLUF must not be trapped in the solder joints, so the viscosity of the WLUF must remain low until the solder fully melts to make metallurgically good interconnections from the center to the corners of the chip. Cross sectional analysis was used to study the geometry of flip chip joints and filler distribution in the perimeter and the center of the chip. It was confirmed that solder joints were metallurgically good with no filler entrapment and that the filler was uniformly distributed. Non destructive X-ray images showed that there was no solder joint bridging in the entire chip area. C-SAM (C-Mode Scanning Acoustic Microscopy) confirmed that the integrity of the BEOL layer was preserved and that any WLUF voids that existed after bonding had been eliminated after full cure under hydrostatic pressure.

High performance wafer level underfill material with high filler loading

A new wafer level underfill material with filler content of 60 weight % was developed for high performance flip chip applications with lead free solder bumps. Systematic optimization of the viscosity behavior led to good spin coat ability even for the material with high filler loading. The material can be applied onto the bumped wafer with high uniformity up to a thickness of 100 |xm by spin coating. The thickness variation was less than 5%. Additionally, void reduction in the package was realized by optimizing the curing process. By controlling the viscosity during the post-curing step voids in the package can be eliminated. Finally, the package with the new wafer level underfill material exhibited good reliability including during thermal cycling.

Mixing, rheology, and stability of highly filled thermal pastes

Thermal pastes play an important role in transmitting heat generated by an integrated circuit chip from its back side to a cooling cap or heat sink which transfers the heat to the environment. Most thermal pastes are formulations of solid, thermally conducting particles in a liquid matrix loaded to very high solids content. The mixing process for such pastes is complex but important, since it determines several of the paste properties. In particular, paste rheology is related to the work imparted to the paste during the mixing process. It determines the minimum bondline between solid surfaces that can be attained with a particular paste during the assembly process, which is essentially a squeeze flow process. Paste stability depends on the amount of entrapped air incorporated during the mixing process; this is demonstrated by infrared (IR) visualization of the degradation of air-containing paste in a computer-chip-heat-sink gap and the absence of this degradation mechanism in vacuum-mixed paste. This paper describes two different mixing processes for highly filled thermal pastes, the associated changes in their rheological behavior, and paste degradation in chip-heat-sink gaps during thermal stressing.

Adhesion studies of polyimide films using a surface acoustic wave sensor

The feasibility of using a surface acoustic wave (SAW) sensor as a novel, nondestructive evaluation (NDE) technique for studying the relative adhesion of thin polyimide (PI) films on quartz (SiO2) has been examined. PI films are of interest because of their widespread use in microelectronics, where there is a continuing need for improved film properties such as the dielectric constant and adhesion. A dual delay linc SAW sensor was used to study the effect of humidity on the PI-quartz interface. The results show clear differences in the comparative SAW humidity response for films applied with and without an adhesion promoter and with and without a chromium intermediate layer. Temperature and humidity ageing was observed to have a greater effect on the SAW humidity response for films without adhesion-improving treatments. A theoretical analysis identified changes in the PI film properties as the physical mechanism responsible for the primary SAW sensor response. The properties of the PI film that change as ...

Measurement of relative adhesion and surface properties of polyimide films using a surfce acoustic wave sensor

Abstract A surface acoustic wave (SAW) sensor is used to study the relative-humidity response of thin polyimide films on quartz, where interfacial and surface properties are varied. The results show differences in the comparative SAW humidity response for films applied with and without adhesion promoter and with and without a chromium interface layer deposited between the substrate and the polyimide film after temperature and humidity aging. Polyimide films were examined that were both sputter cleaned and non-sputter cleaned. The humidity response is particularly sensitive to the surface treatment of the polyimide film. A theoretical analysis has been done to obtain information on the physical mechanisms responsible for the SAW sensor humidity response. The analysis identifies three primary film properties that can influence this response. These properties are changes in density, elastic constants and stress of the film as a function of humidity. The more dominant of these factors appear to be density and elstic-constant changes.