Nancy C. LaBianca

Micromachining applications of a high resolution ultrathick photoresist

This article describes a new negative‐tone photoresist, SU‐8, for ultrathick layer applications. An aspect ratio of 10:1 has been achieved using near‐ultraviolet lithography in a 200‐μm‐thick layer. The use of this resist for building tall micromechanical structures by deep silicon reactive‐ion etching and electroplating is demonstrated. Using SU‐8 stencils, etched depths of ≳200 μm in Si and electroplated 130‐μm‐thick Au structures with near‐vertical sidewalls have been achieved.

Negative photoresists for optical lithography

Negative photoresists are materials that become insoluble in developing solutions when exposed to optical radiation. They were the first systems used to pattern semiconductor devices, and still comprise the largest segment of the photoresist industry because they are widely used to define the circuitry in printed wiring boards. However, the current use of negative resists in the semiconductor industry has been limited by past difficulties in achieving high-resolution patterns. Recent advances in the chemistry of negative-resist systems, however, have provided materials with wide processing latitude and high resolution that are used to manufacture IBMs advanced CMOS devices and to achieve high-aspect-ratio patterns for micromachining applications. This paper provides an overview of the history and chemistry of negative-resist systems and their development in IBM.

A Practical Implementation of Silicon Microchannel Coolers for High Power Chips

This paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance 10.5 C-mm2 /W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of <35kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300W/cm2. Coolers of this design should be able to cool chips with average power densities of 400W/cm2 or more

High-aspect-ratio resist for thick-film applications

In recent years, increased activity in micromachining has driven the need for high aspect ratio thick films resist systems. This paper discusses a new epoxy based resist that can be used to achieve high aspect ratios (> 10:1) using UV lithography. The resulting negative resist system provides sharp, clean images in thick films (> 200 micrometers ). Because of the high aspect ratio and short exposure times, this material may be a viable candidate for producing the images required for micromachined parts. The resist images exhibit straight sidewalls and developed patterns, have excellent thermal stability, good adhesion, and chemical resistance. The high aspect ratio and high thermal stability make these epoxy resists suitable for other packaging applications such as plating stencils and optical wave guides.

A practical implementation of silicon microchannel coolers for high power chips

The paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance of 10.5 C-mm/sup 2//W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of less than 35 kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300 W/cm/sup 2/. Coolers of this design should be able to cool chips with average power densities of 400 W/cm/sup 2/ or more.

Water soluble conducting polyanilines: Applications in lithography

A new class of water soluble conducting polyanilines has been developed. This is accomplished by oxidatively polymerizing aniline monomers on a template such as a polymeric acid. The resulting polyanilines readily dissolve in water. These materials can be applied as removable discharge layers for electron‐beam lithography and for mask inspection by scanning electron microscopy. They can be spin‐applied directly on top of resists without any interfacial problems. Image distortion as a result of charging during resist exposure is not observed with these materials. After exposure the polyaniline is readily and cleanly removed during the resist develop. By incorporating cross‐linkable functionality on the polyaniline backbone, water soluble polyanilines that are radiation curable are attained. Upon irradiation these materials cross‐link and become insoluble and thus can be utilized as permanent conducting coatings for electrostatic discharge applications. In addition, the cross‐linkable polyanilines can be us...

Efficient waveguide-integrated tunnel junction detectors at 1.6 µm

Near-infrared detectors based on metal-insulator-metal tunnel junctions integrated with planarized silicon nanowire waveguides are presented, which we believe to be the first of their kind. The junction is coupled to the waveguide via a thin-film metal antenna feeding a plasmonic travelling wave structure that includes the tunnel junction. These devices are inherently broadband; the design presented here operates throughout the 1500-1700 nm region. Careful design of the antenna and travelling wave region substantially eliminates losses due to poor mode matching and RC rolloff, allowing efficient operation. The antennas are made from multilayer stacks of gold and nickel, and the active devices are Ni-NiO-Ni edge junctions. The waveguides are made via shallow trench isolation technology, resulting in a planar oxide surface with the waveguides buried a few nanometres beneath.The antennas are fabricated using directional deposition through a suspended Ge shadow mask, using a single level of electron-beam lithography. The waveguides are patterned with conventional 248-nm optical lithography and reactive-ion etching, then planarized using shallow-trench isolation technology. We also present measurements showing overall quantum efficiencies of 6% (responsivity 0.08 A/W at 1.605 mum), thus demonstrating that the previously very low overall quantum efficiencies reported for antenna-coupled tunnel junction devices are due to poor electromagnetic coupling and poor choices of antenna metal, not to any inherent limitations of the technology.

Ultrafine-pitch C2 flip chip interconnections with solder-capped Cu pillar bumps

PoP structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch of less than 80 µm or less, an ultra-fine-pitch flip chip interconnection technique is required. C4 flip chip technology is widely used in area array flip chip packages, but it is not suitable in the ultrafine-pitch flip chips because the C4 solder bumps melt and collapse on the wide opening Cu pads. Although the industry uses ultrafine-pitch interconnections between Au stud bumps on a chip and Sn/Ag pre-solder on a carrier, this flip chip technique has two major problems. One is that the need for bumps on both die and carrier drives up material costs. The other is that the long bonding process time required in the individual flip chip bonding process with associated heating and cooling steps demands large investments in equipment. To address these problems, we developed the mount and reflow with no-clean flux processes, and new interconnection techniques were developed with Cu pillars and Sn/Ag solder bumps on Al pads for wirebonding, were developed. It is very easy to control the gap between die and substrate by adjusting the Cu pillar height. Since it is unnecessary to control the collapse of the solder bumps, we call this the C2 process for direct Chip Connection (C2). The C2 bumps are connected to Cu substrate pads, which are a surface treated with OSP (Organic Solder Preservative), with reflow and no-clean processes. This technology creates the SMT/Flip Chip hybrid assembly for SoP (System on Package) use. We have produced 50 µm-pitch C2 interconnections and tested their reliability. The interconnection resistance increase caused by the reliability testing is quite small. It is clear that C2 flip chip technology provides robust solder connections at low cost. Also the C2 structure with a low-k device was evaluated and no failures were observed at 1,500 cycles in the thermal cycle test. This indicates that low-k C2 structures seem robust. For finer pitch flip chip interconnections, a wafer-level underfill process is needed to overcome the limitations of the standard capillary underfill process for ultra-narrow spaces. To date, a wafer- level underfill process exists for the C2 process with an 80-µm pitch. In addition to fine pitch interconnections, a die thickness of 70 µm is required to reduce the final stack height. Such thin die cannot be processed by the C2 process because such dies slip too easily during the reflow process. To resolve this issue, a Post-Encapsulation Grinding (PEG) method was developed. In this method the die is ground to less than 70 µm after joining and underfilling. This report presents the PEG method and reliability test results for die thicknesses 20 µm, 70 µm and 150 µm.

The over-bump applied resin wafer-level underfill process: Process, material and reliability

The over bump applied resin (OBAR) process is a wafer-level underfill (WLUF) process in which a filled resin is applied over the bumps of a wafer and, dried. The wafer is diced into coated chips which are aligned and joined to a substrate resulting in an underfilled flip chip package. This process has been evaluated by IBM on several test vehicles in close cooperation with Henkel (formerly Abelstik) who developed a material specifically to fit this process. The critical steps to make this technology work are alignment of OBAR coated chip to a substrate, elimination of significant voids, formation of a fillet with appropriate shape and size, fluxing and solder joining. The reliability of the material was evaluated after capping and BGA (Ball Grid Array) attach through JEDEC level 3 preconditioning followed by DTC (deep thermal cycling), T&H (temperature and humidity), and HTS (high temperature storage). While some improvements are still needed, the OBAR process has been shown to be a viable alternative to capillary underfill application.

Development of conductive adhesive materials for via fill applications

As mobile computing and telecommunication electronics are spreading fast, a demand for microelectronics packaging schemes for high density, fine pitch, high performance and low cost becomes even more severe. Specifically, the conventional printed circuit board (PCB) with plated-through-hole (PTH) vias is difficult to justify its manufacturing cost as well as the packaging density requirement. To meet this challenge, several new manufacturing schemes of high density and high performance PCB have been recently introduced such as surface laminar circuit (SLC), any layer inner via hole (ALIVH) and others. This new PCB fabrication process is categorized as sequential build-up (SBU) or build-up multilayer (BUM) using laminate-based substrates, where via holes are filled with a conductive paste material to make reliable vertical or Z-interconnects. In this paper, a new electrically conducting paste material to be used for via filling is introduced. The new conducting material consists of a conducting filler powder coated with a low melting point metal or alloy, a mixture of several thermoset resins, and other minor organic additives. By varying the filler content and resin chemistry, several formulations have been produced to fill via holes with a high aspect ratio. Via fill experiments have been performed to demonstrate void-free microstructure with good electrical continuity. Various bulk properties such as thermal, electrical and mechanical have also been characterized to understand the material behavior during via filling as well as the field service.