Colin J. Brodsky

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

The 45-nm technology, called 12S and developed for IBM POWER7®, is an extremely robust and versatile technology platform that allows for a rich set of features that include embedded dynamic random access memory (DRAM), performance and dense static RAM (SRAM), a trench-based decoupling capacitor, a comprehensive device menu, and a high-performance hierarchical back-end interconnect scheme, all built on a silicon-on-insulator (SOI) substrate. Embedded DRAM was implemented for production in high-performance SOI for the first time and allowed us to leapfrog two generations of conventional SRAM densities. Immersion lithography was also employed for the first time in 45-nm IBM products. Our 45-nm design point represents a judicious leverage of silicon oxynitride dielectrics, scaled device technology, and rich features to yield chip-level performance enhancement of more than 50%, compared with our 65-nm node at comparable or less power. This paper describes the salient features of this technology node, the process architecture, the device design rationale, and the process design interactions.

Silicon containing polymer in applications for 193 nm high NA lithography processes

The ability to extend 193 nm lithography resolution depends on increasing the numerical aperture (NA) of the exposure system, resulting in smaller depth of focus, which subsequently requires use of thinner photoresists. Bottom antireflective coatings (BARCs) are a necessity, but the organic composition of current 193 nm BARCs offers poor etch selectivity to the photoresist. As a result, image transfer with thin resists is becoming increasingly difficult. It is also more challenging to control reflectivity at high numerical apertures with a thin, single layer BARC. To address these issues, IBM has developed a new class of silicon containing BARCs. These materials exhibit high etch selectivity that will significantly improve the performance of high NA 193 nm lithography. The incorporation of silicon in the backbone of the polymers comprising these BARCS affords a high etch selectivity to conventional organic resists and therefore these polymers can be used as thick planarizing BARCs. The optical constants of these BARCs have been tuned to provide good reflectivity control at NA > 1.2 These materials can also be used as part of a dual layer BARC scheme composed of the thin organosilicon based BARC coated over a planarizing organic underlayer. This scheme has also been optically tuned to provide reflectivity suppression at high incident angles. By utilizing a thick BARC, a novel contact hole shrink process is enabled that allows tapering of the sidewall angle and controlling the post-etch critical dimension (CD) bias. Structures of the silicon containing polymer, formulation chemistry, optical tunability, lithography at high NA and RIE pattern transfer are reported.

Process Window Centering for 22 nm lithography

Process window centering (PWC) is an efficient methodology to validate or adjust and center the overall process window for a particular lithography layer by detecting systematic and random defects. The PWC methodology incorporates a defect inspection and analysis of the entire die that can be automated to provide timely results. This makes it a good compromise between focus exposure matrix, where centering is based only on critical dimension measurements of a few specific structures and process window qualification which provides very detailed defect inspection and analysis, but is more time consuming for lithography centering. This paper describes the application of the PWC methodology for 22 nm lithography centering in IBMs Albany, NY, and East Fishkill, NY, development facilities using KLA-Tencors 28xx brightfield defect inspection system.

Lithography budget analysis at the process module level

A simple experimentally characterized lumped-parameter budget model is developed with the goal of quantifying the most significant components of critical dimension (CD) variation through an integrated process module. Tracked components include mask fabrication budgets, mask error factor, scanner field variation, optical proximity correction error, CD errors over chip topography, wafer-to-wafer and lot-to-lot variation. The components of variation are quantified for lithography and etch where appropriate and are fed into a simple interaction model to construct an overall patterning module CD budget. Normalized experimental results for this budget analysis are presented for 65 nm technology node contact patterning processes.

Topography induced defocus with a scanning exposure system

Our case study experimentally gauges the defocus component induced by a step in the exposure field substrate, with the edge of the step aligned parallel to the scanning slit. Such steps frequently occur at the border of different chiplets or process monitors within one exposure field. A common assumption is that a step-and-scan imaging system can correct for the majority of such topography, since the wafer is dynamically leveled under the static image plane as it is scanned. Our results show that the range of defocus approaches about 85% of the actual step height and thus contributes significantly to the overall focusing variance. This area on the wafer in which defocus can be observed extends by more than 3mm to both sides of the step. In the same area a degradation of imaging fidelity can be observed in the form of exaggerated proximity effects.

Strategies for single patterning of contacts for 32nm and 28nm technology

As 193 nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28 nm technology nodes has been greatly facilitated by just-in-time introduction of new process enablers that allow the support of flexible foundry-oriented ground rules alongside high-performance technology, without inhibiting migration to a single-pass patterning process. The incorporation of device based performance metrics along with rigorous patterning and structural variability studies were critical in the evaluation of material innovation for improved resolution and CD shrink. Additionally novel design changes for single patterning along new capability in data preparation were both assessed to leverage minimal impact of implementation of a single patterning contact process into the existing 32nm and 28nm technology programs [1].

Contact patterning strategies for 32nm and 28nm technology

As 193 nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28 nm technology nodes has been greatly facilitated by just-in-time introduction of new process enablers that allow the simultaneous support of flexible foundry-oriented ground rules alongside highperformance technology, while also migrating to a single-pass patterning process. The incorporation of device based performance metrics along with rigorous patterning and structural variability studies were critical in the evaluation of material innovation for improved resolution and CD shrink along with novel data preparation flows utilizing aggressive strategies for SRAF insertion and retargeting.

Determining DOF requirements needed to meet technology process assumptions

Depth of Focus (DOF) and exposure latitude requirements have long been ambiguous. Techniques range from scaling values from previous generations to summing individual components from the scanner. Even more ambiguous is what critical dimension (CD) variation can be allowed to originate from dose and focus variation. In this paper we discuss a comprehensive approach to measuring focus variation that a process must be capable of handling. We also describe a detailed methodology to determine how much CD variation can come from dose and focus variation. This includes examples of the statistics used to combine individual components of CD, dose and focus variation.

Rinse additives for defect suppression in 193-nm and 248-nm lithogrophy

Satellite spot defects are a class of defects widely observed in photoresist processing in 248 nm and 193 nm lithography. These defects become more and more significant as the feature sizes shrink and can potentially become “killer” defects, leading to bridging between lines and/or blocking vias. Traditional potential solutions (i.e., optimization of development rinse step) have yielded improvements in the past but did not eliminate the problem. The use of water-soluble topcoat layers was shown to eliminate these defects but it imposes limitations on throughput and cost and it is incompatible with 157 nm lithography and 193 nm immersion schemes. In this work, we report the use of aqueous surfactant solutions for the suppression of defects in 248 nm and 193 nm lithography, with emphasis on satellite spot defects. Suppression of total defects by up to ~99% and practically complete elimination of satellite spot defects were achieved by use of aqueous surfactant solutions for various resists. A handful of materials that can be incorporated into rinse solution for the successful elimination of blob defects in a variety of resists were identified. It was determined that the two most important factors that enable successful defect elimination are the surfactant concentration and the extent of surfactant adsorption to specific resist systems.

Highly etch-selective spin-on bottom antireflective coating for use in 193-nm lithography and beyond

Extending 193nm lithography to well below 100nm resolution will depend on high NA tooling coupled with thin resist processing. Semiconductor manufacturing uses BARCs (Bottom Antireflective Coating) based on organic spin coatable polymers, to improve the resolution by absorbing light that otherwise will be reflected back into the resist. However, the use of organic BARCs for patterning sub 100nm features will be limited due to poor etch selectivity to the photo resist. IBM has developed a new class of polymers that can function as planarizing BARCs. These materials show an etch selectivity to the photo resist in excess of 3:1 in fluorocarbon based ARC-open RIE chemistry. The hardmask properties of these materials for oxide open are equivalent to typical resists. Furthermore these materials can be implemented like organic ARCs and are stripped in resist strips available in manufacturing. Basic materials characterization data, optical tunability, lithographic performance with different resists, process window data, and complete integration schemes will be presented.