Scott D. Allen

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.

Effect of thin-film imaging on line edge roughness transfer to underlayers during etch processes

For the patterning of sub-100 nm features, a clear understanding of the origin and control of line edge roughness (LER) is extremely desirable, from a fundamental as well as a manufacturing perspective. With the migration to thin photoresists coupled with bottom antireflective coating (ARC)-hardmask underlayers, LER analysis of the developed resist structures is perhaps an inaccurate representation of the substrate roughness after the etch process, since those underlayers can play a significant role in increasing/decreasing linewidth variations during the image transfer process and hence can impact the device performance. In this article, atomic force microscopy is used to investigate the contribution of the imaging resist sidewall topography to the sidewall roughness of the final etched feature in thin photoresists, ARC, and hardmasks. Resist systems suitable for 248 and 193 nm lithography as well as fluorine-containing resists were processed using N2-H2 or fluorocarbon plasma etch. It is shown that the ...

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high performance 0.65/spl mu/m/sup 2/ SRAM cell is also presented. SOI allows the SRAM cell to use Metal 1 instead of Metal 2 for bit-line wiring, which lowers the capacitance and improves access times. A functional dual-core microprocessor test chip containing 76Mb SRAM cache and key execution units has been fabricated.

A 0.127 μm 2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications

The authors present a 65nm embedded DRAM cell (0.127 μm2 cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL). The cell utilizes a low-leakage 2.2-nm gate oxide pass transistor and a deep trench capacitor. A trench side wall spacer process enables a simplified collarless process. Connection to the buried plate is realized by silicided substrate guardrings with fully landed tungsten contacts. The bitline structure and the deep trench capacitor are designed for high transfer ratio and low RC constant which ensure high performance and sufficient sensing signal. The pass transistor is strain engineered to boost on current and employs optimized S/D junctions to help attain sub-pA off current. This technology has produced fully-functional 2Mb prototype embedded macros with sub-1.5ns latency and sub-2ns random cycle times for on-processor caches. The low leakage device developed also enables for the first time a low standby power SOI technology

Hardmask technology for sub-100-nm lithographic imaging

The importance of hardmask technology is becoming increasingly evident as the demand for high-resolution imaging dictates the use of ever-thinner resist films. An appropriately designed etch resistant hardmask used in conjunction with a thin resist can provide the combined lithographic and etch performance needed for sub-100 nm device fabrication. We have developed a silicon-based, plasma-enhanced chemical vapor deposition (PECVD) prepared material that performs both as an antireflective coating (ARC) and a hardmask and thus enables the use of thin resists for device fabrication. This ARC/hardmask material offers several advantages over organic bottom antireflective coatings (BARC). These benefits include excellent tunability of the materials optical properties, which allows superior substrate reflectivity control, and high etch selectivity to resist, exceeding 2:1. In addition, this material can serve as an effective hardmask etch barrier during the plasma etching of dielectric stacks, as the underlying silicon oxide etches eight times faster than this material in typical fluorocarbon plasma. These properties enable the pattering of features in 1-2 μm dielectric stacks using thin resists, imaging that would otherwise be impossible with conventional processing. Potential extendibility of this approach to feature sizes below 100nm has been also evaluated. High resolution images as small as 50nm, have been transferred into a 300nm thick SiO2 layer by using Si ARC/hardmask material as an etch mask. Lithographic performance and etch characteristics of a thin resist process over both single layer and index-graded ARC/hardmask materials will be shown.

Silicon containing polymer in applications for 193 nm high NA lithography processes

The ability to extend 193 nm lithography resolution depends on increasing the numerical aperture (NA) of the exposure system, resulting in smaller depth of focus, which subsequently requires use of thinner photoresists. Bottom antireflective coatings (BARCs) are a necessity, but the organic composition of current 193 nm BARCs offers poor etch selectivity to the photoresist. As a result, image transfer with thin resists is becoming increasingly difficult. It is also more challenging to control reflectivity at high numerical apertures with a thin, single layer BARC. To address these issues, IBM has developed a new class of silicon containing BARCs. These materials exhibit high etch selectivity that will significantly improve the performance of high NA 193 nm lithography. The incorporation of silicon in the backbone of the polymers comprising these BARCS affords a high etch selectivity to conventional organic resists and therefore these polymers can be used as thick planarizing BARCs. The optical constants of these BARCs have been tuned to provide good reflectivity control at NA > 1.2 These materials can also be used as part of a dual layer BARC scheme composed of the thin organosilicon based BARC coated over a planarizing organic underlayer. This scheme has also been optically tuned to provide reflectivity suppression at high incident angles. By utilizing a thick BARC, a novel contact hole shrink process is enabled that allows tapering of the sidewall angle and controlling the post-etch critical dimension (CD) bias. Structures of the silicon containing polymer, formulation chemistry, optical tunability, lithography at high NA and RIE pattern transfer are reported.

Integrated non-SO2 underlayer and improved line-edge-roughness dielectric etch process using 193nm bilayer resist

We present an integrated reactive ion etch (RIE) process using bilayer (a top imaging layer and a bottom underlayer) thin film imaging system to push the limits of 193nm wavelength photolithography. Minimizing the line-edge roughness (LER) and maintaining the critical dimension (CD) of the transferred pattern are important in high-resolution RIE. Along with LER and CD issues and shrinking ground rules, deleterious effects of SO2 in the underlayer etch chemistry necessitated the development of non-SO2 chemistry. Thus a N2–H2–CO chemistry was developed and integrated with the etch process of underlying borophosphosilicate glass using Ar–O2–C4F8–CO–CH3F chemistry.

Controlling line-edge roughness and reactive ion etch lag in sub-150 nm features in borophosphosilicate glass

We have developed a reactive ion etch (RIE) process in borophosphosilicate glass (BPSG) for 150 nm line-and-space features, where line-edge roughness (LER) complemented with RIE lag becomes a major issue. Effect of flow rates and carbon-to-fluorine atomic ratio of fluorohydrocarbon gases was utilized to achieve acceptable process window allowing lower radio frequency powers therefore obtaining acceptable LER and RIE lag in the high-resolution features etched into BPSG.

Highly etch-selective spin-on bottom antireflective coating for use in 193-nm lithography and beyond

Extending 193nm lithography to well below 100nm resolution will depend on high NA tooling coupled with thin resist processing. Semiconductor manufacturing uses BARCs (Bottom Antireflective Coating) based on organic spin coatable polymers, to improve the resolution by absorbing light that otherwise will be reflected back into the resist. However, the use of organic BARCs for patterning sub 100nm features will be limited due to poor etch selectivity to the photo resist. IBM has developed a new class of polymers that can function as planarizing BARCs. These materials show an etch selectivity to the photo resist in excess of 3:1 in fluorocarbon based ARC-open RIE chemistry. The hardmask properties of these materials for oxide open are equivalent to typical resists. Furthermore these materials can be implemented like organic ARCs and are stripped in resist strips available in manufacturing. Basic materials characterization data, optical tunability, lithographic performance with different resists, process window data, and complete integration schemes will be presented.