Wai-kin Li

Resist freezing process for double exposure lithography

In this study, we have developed a thermal freezing process to prevent intermixing between 1st patterned positive resist and 2nd positive resist. Based on solvent solubility switch characteristic of polymer after higher temperature bake, a prototype of polymer consisting of methyladmantane mathacrylate, norbornanecarbo lactone mathacrylate and hydroxyl admantane mathacrylate was selected for resist-on-resist double exposure experiment to prevent the intermixing between layers. Photo sensitivity shifting of this prototype resist after post develop bake further facilitates the design by preventing 1st layer resist distortion from 2nd exposure. Lastly, through composition and formulation optimization, 35nm L/S patterns were successfully demonstrated by using a 1.2NA stepper.

Determining DOF requirements needed to meet technology process assumptions

Depth of Focus (DOF) and exposure latitude requirements have long been ambiguous. Techniques range from scaling values from previous generations to summing individual components from the scanner. Even more ambiguous is what critical dimension (CD) variation can be allowed to originate from dose and focus variation. In this paper we discuss a comprehensive approach to measuring focus variation that a process must be capable of handling. We also describe a detailed methodology to determine how much CD variation can come from dose and focus variation. This includes examples of the statistics used to combine individual components of CD, dose and focus variation.

Focus improvement with NIR absorbing underlayer attenuating substructure reflectivity

Process dependent focus leveling errors occur in photolithography when there is unpredicted reflectivity originating from multilayer structures on the fully integrated process wafer. The typical wavelength used in optical focus sensors is in the near infrared (NIR) range which is highly transparent to most dielectric materials. Consequently, the reflected light from underlying structures perturbs the accuracy of the leveling signal reflected from resist surface. To alleviate this issue, air-gauge focus sensors have been used to measure the wafer surface topography for an in-situ calibration to correct the focus leveling error. Using an air-gauge sensor is a slow process and a throughput detractor. Therefore, an NIR-absorbing underlayer has been developed for easy insertion into existing resist coating processes. It has been demonstrated that the air-gauge sensor can be turned off without showing any degradation in leveling data or litho performance on back end of line (BEOL) integrated wafers.

From Process Assumptions to Development to Manufacturing

A tool has been developed that can be used to characterize or validate a BEOL interconnect technology. It connects various process assumptions directly to electrical parameters including resistance. The resistance of narrow copper lines is becoming a challenging parameter, not only in terms of controlling its value but also understanding the underlying mechanisms. The resistance was measured for 45nm-node interconnects and compared to the theory of electron scattering. This work will demonstrate how valuable it is to directly link the electrical models to the physical on-wafer dimensions and in turn to the process assumptions. For example, one can generate a tolerance pareto for physical and or electrical parameters that immediately identifies those process sectors that have the largest contribution to the overall tolerance. It also can be used to easily generate resistance versus capacitance plots which provide a good BEOL performance gauge. Several examples for 45nm BEOL will be given to demonstrate the value of these tools.

Impact of mask CD error on OPC performance for 65nm technology M1 level

As lithography pushes to smaller and smaller features under the guidance of Moores Law, patterned features smaller than the wavelength of light must be routinely manufactured. Lithographic yield in this domain is directly improved with the application of OPC (Optical and Process Correction) to the pattern data. Such corrections generally assume that the mask can reproduce these features exactly. The Mask Error Enhancement Factor (MEEF) serves to amplify mask errors, and can reduce the benefits of OPC in some circumstances. In this paper, we present the characterization of the MEEF for 65nm technology attenuated phase shift mask to figure out how to better set mask specs from an OPC perspective and how to measure the masks relative to these specs and try to figure out new ways to reduce model sensitivity to mask deviations for metal level.

Is model-based optical proximity correction ready for manufacturing? Study on 0.12- and 0.175-μm DRAM technology

Two full-chip OPC approaches, a traditional rule-based approach and a more recent model-based approach are compared on DRAM applications using both ArF and KrF lithography, with off-axis illumination and phase shift masks. The similarities and differences between these two OPC approaches are compared in detail with selected one- and two-dimensional layout situations. Our results from the model-based approach show good line width control for one- dimensional structures and improved line-end printing for two-dimensional structures; however, results also show severe process window limitations for some layouts. The cause of the process window limitations with the model-based approach are discussed. To address the process window limitations in the model-based approach, a rule-based pre- correction was used to ensure adequate process window at deviated dose and focus conditions. With pre-correction combined with the model-based approach, our wafer data shows good correction quality and process window.