Congyin Shi

Unipolar

In this letter, a reproducible unipolar resistive change memory (RRAM) based on TaOx was successfully fabricated through electrode design. The fabricated unipolar RRAM exhibits lower switching voltages, fast switching speed of less than 80 ns, excellent retention capabilities, and stable cycling behaviors. Moreover, the role of top-electrode material on the resistive switching mode polarity of TaOx-based RRAM was verified by comparative experiments. Analysis about the electrode effect on the resistive switching mode polarity of TaOx-based RRAM with the theory of Gibbs free energy may provide some guidelines for the design of unipolar metal-oxide-based RRAM.

\hbox{TaO}_{x}

This paper presents a generic-purpose solution of highly power-efficient active-RC filters, which is suitable for analog baseband with wide bandwidth-range from several mega-Hz to hundreds of mega-Hz in wireless receivers. A 260 μA 7-20 MHz 6th-order active-RC low-bandwidth low-pass filter (LBW-LPF) and a 2.3 mA 240-500 MHz 6th-order active-RC high-bandwidth low-pass filter (HBW-LPF) are implemented in a standard 0.18 μm CMOS process to demonstrate this versatile solution. Highly power-efficient push-pull opamps with 30-to-35 dB gain are adopted for the filters, which allow us to focus on extending the bandwidth and reducing the power consumption. The push-pull opamp with adaptive-biased and pole-cancellation push-pull source follower (APP-SF) as the buffer stage is proposed to greatly reduce the power consumption and effectively extend the bandwidth. An adaptive bias mechanism is also proposed to tolerate the PVT variations for the opamps. In addition, the GBW compensation and the Q-degrading scheme are adopted to relax the opamp GBW requirement, further reducing the power dissipation. The LBW-LPF only consumes 260 μA current from 1.8 V supply, achieves 14.4 dBm in-band IIP3 and 66.2 nV/√ Hz IRN density, and occupies 0.21 mm 2 silicon area without pads. The HBW-LPF merely dissipates 2.3 mA current from 1.8 V supply, achieves 11.3 dBm in-band IIP3 and 13.1 nV/√ Hz IRN density, and occupies 0.23 mm 2 silicon area without pads.

-Based Resistive Change Memory Realized With Electrode Engineering

A low distortion sinusoidal waveform synthesizer architecture is proposed. The synthesizer utilizes 50% duty cycle and differential-mode circuitry to eliminate the even order harmonics, and it also implements a 5-phase 3-amplitude harmonic cancellation technique to suppress the 3rd, 5th, 7th, and 9th order harmonics. The compact system architecture consists of a 12-phase ring oscillator, a weighted resistor summing network, and an RC output filter. Phase shifters are adopted in the ring oscillator to enable the control of an external harmonic cancellation optimization algorithm. The proposed application of the optimization algorithm compensates the errors in the circuit and further improves the linearity of the output waveforms. This synthesizer is fabricated in 180 nm standard CMOS technology, occupies a 0.08 mm2 silicon area and achieves the spur-free dynamic range (SFDR) of 59 to 70 dBc from 150 to 850 MHz after the optimization procedure. It can operate from a 1 to 1.8 V supply voltage and achieve a power consumption from 9.11 to 57 mW.

Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps

This paper presents a 6th-order active-RC low-pass filter with 240 MHz to 500 MHz tunable bandwidth, which is suitable for the ultra-wideband transceivers. The filter consumes only 2.3 mA from 1.8 V supply voltage, which is mainly attributed to the proposed highly power-efficient operational amplifier (Opamp) with an adaptive-biased pole-cancellation push-pull source follower as the buffer stage to drastically extend the bandwidth. The technique of high-frequency common-mode rejection using parasitic capacitor is utilized to guarantee the Opamp stability. In addition, the filter adopts the Q-tuning technique and Opamp GBW compensation mechanism, which relax the GBW requirement of the Opamp to further reduce the power consumption. The filter achieves 1.36 pW/pole/Hz normalized power, 13.1 nVA√Hz input-referred noise density, 15.9 dBm in-band IIP3, and 34 dBm out-of-band IIP3, respectively. The chip is fabricated in a standard 0.18 μm CMOS process, and occupies 0.23 mm2 silicon area without pads.

150–850 MHz High-Linearity Sine-wave Synthesizer Architecture Based on FIR Filter Approach and SFDR Optimization

This paper presents an ultra-low power 6th-order 7MHz-to−20MHz tunable active-RC low-pass filter. Due to the proposed highly power-efficient Opamp, the filter only consumes 0.47 mA power from 1.8 V supply voltage, corresponding to 3.86 pW/Hz/pole normalized power. The Opamp utilizes an adaptive-biased pole-cancellation push-pull buffer to greatly reduce the power consumption. An adaptive bias circuit is proposed to cooperate with the Opamp to tolerate the PVT variations. The filter achieves 20.9 dBm in-band IIP3, and 298 µVrms integrated input-referred noise. The chip is fabricated in a standard 0.18 µm CMOS process, and occupies 0.21 mm2 silicon area without ESD/pads.

A 2.3mA 240-to-500MHz 6 th -order active-RC low-pass filter for ultra-wideband transceiver

In this paper, a unipolar resistive change memory (RRAM) based on TaOx has been successfully fabricated. The fabricated unipolar RRAM exhibits lower switching voltages without any forming process, fast switching speed, good retention performance even under high temperature baking and stable cycling behavior. Multilevel of data storage can also be achieved by voltage control during the reset process. In addition, the current compliance (CC) effect on the behavior of the device has also been investigated. Based on the measurements, the switching voltages/currents and the low resistance state (LRS) of the device have little dependence on CC, which can effectively simplify RRAM circuit design. Resistive switching polarity dependence on the bi-layer structure has also been analyzed with comparative experiments.

A 0.47mW 6 th -order 20MHz active filter using highly power-efficient Opamp

This paper presents a direct-conversion DTV tuner for both VHF and UHF bands. The proposed tuner achieves a noise figure of 2.5-3.5 dB at VHF band and 2-3 dB at UHF band while the LNA consumes only 3.5 mW. An external band-pass LC filter is adopted for RF pre-filtering and providing DC conduction path for noise cancelling balun LNA. The system-level co-design of the LNA and pre-selecting filter further help to obtain 33 dB third-order harmonic rejection ratio without using harmonic rejection mixers. A quantization-noise-compensated fractional- N frequency synthesizer is implemented, achieving 0.5 ° integrated phase error (1 kHz to 4 MHz) at 666 MHz, and suppressing out-of-band ΣΔ noise by 20 dB. The proposed PLL injects compensation current into the loop filter during the PFD delay time, which precisely tracks the VCO output frequency. Highly reconfigurable analog baseband with 0.5-4 MHz bandwidth and 6-54 dB gain is integrated. The tuner is implemented in 65 nm CMOS process, occupies an area of 4.2 mm2, and consumes only 72 mW from a 1.2 V voltage supply.

Forming-Less Unipolar TaOx-Based RRAM with Large CC-Independence Range for High Density Memory Applications

In this paper, a high thermal stable TaOx-based RRAM device has been fabricated with TiN as the top electrode. The fabricated device shows good endurance behavior with little fluctuations in voltages and resistance state. Due to the stability of this device, potential for MLC application was also investigated. In addition, the mechanism of the high performance of the device is analyzed with Gibbs free energy based on the TEM-analysis and comparative experiments.

A 4.2 mm

A CMOS phase-locked loop (PLL) which synthesizes frequencies between 474 and 858 MHz in steps of 1 MHz and settles in less than 180 ¿s is presented. This PLL can be implemented as a sub-circuit for a frequency synthesizer which serves for UHF Digital-TV receiver. To realize fast loop settling, integer-N architecture that work with 1 MHz reference frequency is implemented and a novel adaptive frequency calibration (AFC) of programmable dichotomizing coarse tuning technology is integrated. The novel AFC structure uses pulses of 2n times of the PFD¿s reference frequency for counting and comparison. Two multi-band voltage controlled oscillators, which cover 866 to 1468 MHz and 1282 to 1892 MHz separately, are implemented so as to reduce VCO output noise and power consumption by reducing VCO gain on each frequency turning curse. I/Q carriers are generated by VCO output divided by 2. Fabricated in 0.18-¿m CMOS technology, the PLL achieves phase noise of less than -132 dBc/Hz at 1.45 MHz offset.

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A CMOS wideband receiver for BD-Π B2&B3 mode is presented. The chip demonstrates a noise figure of 4.0dB and a 2dB CNR desensitization point of 4dBm at 800MHz GSM blocker. Due to the optimized design of an ESD-protected LNA and a 1/f-noise-reduced high-LO-RF-isolation Mixer, the spurious level is suppressed below −113dBm referred to the RF input. The fractional-N ΣΔ synthesizer obtains LO phase noise of −92dBc/Hz@lKHz and −117dBc/Hz@lMHz, with the reference spurs are below −60dBc. The integrated 4th-order LPF has tunable 7.5MHz/10MHz/15MHz corner frequency. The mixed-signal AGC loop, including 4-bit ADCs, variable gain amplifier and programmable amplifier, achieves 55dB gain dynamic range. The receiver consumes 31mA from a 1.8-V supply voltage while occupying a 5.5-mm2 die area including ESD pads.