Huailin Liao

Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps

This paper presents a generic-purpose solution of highly power-efficient active-RC filters, which is suitable for analog baseband with wide bandwidth-range from several mega-Hz to hundreds of mega-Hz in wireless receivers. A 260 μA 7-20 MHz 6th-order active-RC low-bandwidth low-pass filter (LBW-LPF) and a 2.3 mA 240-500 MHz 6th-order active-RC high-bandwidth low-pass filter (HBW-LPF) are implemented in a standard 0.18 μm CMOS process to demonstrate this versatile solution. Highly power-efficient push-pull opamps with 30-to-35 dB gain are adopted for the filters, which allow us to focus on extending the bandwidth and reducing the power consumption. The push-pull opamp with adaptive-biased and pole-cancellation push-pull source follower (APP-SF) as the buffer stage is proposed to greatly reduce the power consumption and effectively extend the bandwidth. An adaptive bias mechanism is also proposed to tolerate the PVT variations for the opamps. In addition, the GBW compensation and the Q-degrading scheme are adopted to relax the opamp GBW requirement, further reducing the power dissipation. The LBW-LPF only consumes 260 μA current from 1.8 V supply, achieves 14.4 dBm in-band IIP3 and 66.2 nV/√ Hz IRN density, and occupies 0.21 mm 2 silicon area without pads. The HBW-LPF merely dissipates 2.3 mA current from 1.8 V supply, achieves 11.3 dBm in-band IIP3 and 13.1 nV/√ Hz IRN density, and occupies 0.23 mm 2 silicon area without pads.

A Physics-Based Equivalent-Circuit Model for On-Chip Symmetric Transformers With Accurate Substrate Modeling

A physics-based equivalent-circuit model for on-chip symmetric transformers is presented with all the model elements driven from fabrication specifications. Two extra coupled transformer loops are used for each coil to model the parameters of skin effect, proximity effect, and reflective effect of the substrate eddy current, respectively. Model accuracy under free space is first demonstrated using an electromagnetic field solver without considering substrate loss. Several sets of transformers were fabricated on a standard 0.18- mum 1P8M RF CMOS technology to further verify the accuracy and scalability of the proposed model. By careful comparison of S -parameters, coil inductance, quality factor,coupling coefficient, and maximum available gain between measured data and simulated data, model accuracy, and scalability are verified over a wide range of geometry configurations.

A Wideband Predictive “Double- ” Equivalent-Circuit Model for On-Chip Spiral Inductors

A new wideband predictive ldquodouble-pirdquo equivalent-circuit model for on-chip spiral inductors is presented, in which the model parameters are analytically calculated with layout and process parameters. In the model, five major parasitic effects, including skin effect, proximity effect, distributed effect, substrate capacitive loss, and inductive loss, are implemented together. Considering skin effect and proximity effect simultaneously, a new equation of high-frequency resistance is proposed, and accordingly, two coupled transformer loops are developed, respectively, to calculate the network parameters of skin effect, proximity effect, and substrate inductive coupling effect independently. In order to analytically calculate substrate capacitive loss in multiturn inductors, a quasi-linear relationship between capacitive coupling effect and proximity effect is established. A series of inductors with different geometries are fabricated in two standard RFCMOS processes to verify the model. Excellent agreements have been obtained between the measured data and the proposed model within a wide frequency range. Since a clear relationship between circuit components and fabrication parameters is defined, it can precisely predict the performance of the inductors and become more flexible in RFIC design.

A Novel RF LDMOS Fabricated With Standard Foundry Technology

In this letter, a novel LDMOS structure is proposed and experimentally demonstrated with standard foundry CMOS technology. The device features both an inserted oxide layer in the drift region as the ldquoelectric field line absorberrdquo and a high-doped region introduced for action of the RESURF-like structure. The RESURF-Dielectric-region-Inserted LDMOS device with breakdown voltage of about 15 V and peak cutoff frequency of 18 GHz is obtained. The proposed device also exhibits good reliability behavior under high-voltage stressing. The new device is very promising for integrated power amplifier circuit design with the standard CMOS process.

High-

In this letter, a post-CMOS selectively grown porous silicon (SGPS) technique is proposed to improve the Q-factor of the integrated inductor. The inductors are fabricated in a standard RF CMOS process, and porous silicon layers are selectively grown after processing from the backside of the silicon wafer. For a 2.1-nH inductor fabricated in a 1 poly 3 metal 0.35- RF CMOS process, a 105% increase (from 9.5 to 19.4) in peak -factor is achieved. Furthermore, a 2.45-GHz CMOS voltage-controlled oscillator using the proposed SGPS inductor achieves 7.2-dBc phase noise improvement at 100-kHz frequency offset. The characteristics of the SGPS substrate have been extracted using the conventional lump element model, which shows that our SGPS technique increases the substrate impedance by one order magnitude without disturbing the inductor value. These results demonstrate that our post-CMOS SGPS technique is very promising for RF integrated circuit applications.

Q

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the characterization and analysis of this unique one-dimensional nanowire-channel device with three-dimensional surrounding-gate from experiments and simulation, including carrier transport behavior, parasitic effects, noise characteristics, self-heating effect, variability and reliability, which can provide useful information for the GAA device hierarchical modeling and device/circuit co-design.

Integrated Inductor Using Post-CMOS Selectively Grown Porous Silicon (SGPS) Technique for RFIC Applications

A highly reconfigurable merged analog baseband (MABB) with not only tunable bandwidth (BW), gain, and order but also reconfigurable power, noise, and linearity is proposed for multistandard integrated wireless receivers in this brief. The MABB could arrange the total gain to different stages for noise and linearity tradeoffs by introducing the merged biquad topology. To save power, the operational amplifier (Opamp) for the proposed MABB can reduce the GBW, as long as it meets the GBW requirement for different BW, gain, and order. A flexible power-efficient high-GBW Opamp with an adaptive common-mode bias circuit is also proposed for the eighth-order active-RC MABB. The proposed MABB covers a cutoff frequency range from 200 kHz to 20 MHz, whereas the gain could be tuned between 0 and 72 dB. The proposed highly reconfigurable MABB is suitable for multistandard integrated wireless receivers.

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling

A new wideband predictive ldquodouble-pirdquo equivalent-circuit model for on-chip spiral inductors is presented, in which the model parameters are analytically calculated with layout and process parameters. In the model, five major parasitic effects, including skin effect, proximity effect, distributed effect, substrate capacitive loss, and inductive loss, are implemented together. Considering skin effect and proximity effect simultaneously, a new equation of high-frequency resistance is proposed, and accordingly, two coupled transformer loops are developed, respectively, to calculate the network parameters of skin effect, proximity effect, and substrate inductive coupling effect independently. In order to analytically calculate substrate capacitive loss in multiturn inductors, a quasi-linear relationship between capacitive coupling effect and proximity effect is established. A series of inductors with different geometries are fabricated in two standard RFCMOS processes to verify the model. Excellent agreements have been obtained between the measured data and the proposed model within a wide frequency range. Since a clear relationship between circuit components and fabrication parameters is defined, it can precisely predict the performance of the inductors and become more flexible in RFIC design.

Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65- nm CMOS

A new wideband predictive ldquodouble-pirdquo equivalent-circuit model for on-chip spiral inductors is presented, in which the model parameters are analytically calculated with layout and process parameters. In the model, five major parasitic effects, including skin effect, proximity effect, distributed effect, substrate capacitive loss, and inductive loss, are implemented together. Considering skin effect and proximity effect simultaneously, a new equation of high-frequency resistance is proposed, and accordingly, two coupled transformer loops are developed, respectively, to calculate the network parameters of skin effect, proximity effect, and substrate inductive coupling effect independently. In order to analytically calculate substrate capacitive loss in multiturn inductors, a quasi-linear relationship between capacitive coupling effect and proximity effect is established. A series of inductors with different geometries are fabricated in two standard RFCMOS processes to verify the model. Excellent agreements have been obtained between the measured data and the proposed model within a wide frequency range. Since a clear relationship between circuit components and fabrication parameters is defined, it can precisely predict the performance of the inductors and become more flexible in RFIC design.

A Wideband Predictive "Double-π" Equivalent-Circuit Model for On-Chip Spiral Inductors

A 400MHz on-off keying transceiver for medical implant applications is presented. The transceiver achieves ultra-low power and high sensitivity with an analog “quadratic sum” demodulation scheme, which enables the using of a low intermediate frequency and a free-running oscillator for power saving. A new current-reuse structure and an inductor-sharing technique for front-end are also introduced to further reduce power consumption. The transceiver is implemented in 0.18μm CMOS process with 3.18mm2 chip area. At 2 Mbps data rate, the receiver achieves energy efficiency of 1.71nJ/bit with sensitivity of −80.2dBm for 10−3 BER, and the transmitter achieves energy efficiency of 1.53nJ/bit with −2.17dBm output power.