Cornelis Niessen

Low-power operation using self-timed circuits and adaptive scaling of the supply voltage

Recent research has demonstrated that for certain types of applications like sampled audio systems, self-timed circuits can achieve very low power consumption, because unused circuit parts automatically turn into a stand-by mode. Additional savings may be obtained by combining the self-timed circuits with a mechanism that adaptively adjusts the supply voltage to the smallest possible, while maintaining the performance requirements. This paper describes such a mechanism, analyzes the possible power savings, and presents a demonstrator chip that has been fabricated and tested. The idea of voltage scaling has been used previously in synchronous circuits, and the contributions of the present paper are: 1) the combination of supply scaling and self-timed circuitry which has some unique advantages, and 2) the thorough analysis of the power savings that are possible using this technique. >

The Sprite Input Language-an intermediate format for high level synthesis

Describes a simple and powerful input language (intermediate format) for high level synthesis. The language belongs to the class of signalflow graphs. The Sprite Input Language (SIL) encompasses both the applicative constructs on which classical DSP languages like Silage are based, the functional constructs from hardware description languages like ELLA, and the operational constructs from sequential languages like Pascal and C. This is obtained by means of the single token flow model and using sets instead of single values for data modelling. The language is suited for acting as an intermediate language between the various specification languages and the silicon compilation system, as well as a language backbone in the synthesis part of a silicon compiler.<<ETX>>

PIRAMID: an architecture-driven silicon compiler for complex DSP applications

The PIRAMID design system, a silicon compiler for the synthesis of DSP algorithms is described. Starting from a functional specification, a complete VLSI mask layout and a set of test patterns are automatically generated. The designer explores design alternatives by interacting with the compiler, thus finding an implementation that matches performance requirements at minimal hardware cost. Some design examples are presented to demonstrate its viability.<<ETX>>