Craig Hickman

Etch, reticle, and track CD fingerprint corrections with local dose compensation

Meeting a specific CD uniformity roadmap becomes more and more difficult as different budget components affecting CD uniformity fail to meet their requirements. For example, reticle manufacturing is at the edge of its potential, and hotplates impact CD uniformity by design. Also, etch processes must be balanced between optimal settings for varying structures. While work continues to enhance the performance of individual budget components, applying local exposure dose compensation with a scanner can provide a near-term solution for improving CD uniformity. Within the wafer processing chain, only the scanner has the unique capability to influence the final quality across-field and field-to-field in a controlled manner, making it the most effective tool for compensation. This paper describes the subsystems required for dose compensation and presents a solution that allows full integration into an automated fabrication environment. Examples will show that both the reticle contribution as well as the process-induced across-wafer fingerprint, including etch, can be improved by up to 50 percent. This improvement is demonstrated both on test structures and on memory device layers.

A study on the automation of scanner matching

Scanner matching based on CD or patterning contours has been demonstrated in past works. All of these published works require extensive wafer metrology. In contrast, this work extends a previously proposed optical pattern matching method that requires little metrology by adding the component requirements and the procedure for creating an automation flow. In a test case, we matched an ASML XT:1900i using a DOE to an ASML NXT:1950i scanner using FlexRay. The matching was conducted on a 4x nm process test layer as a development vehicle for the 2x nm product nodes. The paper summarizes the before and after matching data and analysis, with future opportunities for improvements suggested.

Wafer quality analysis of various scribe line mark designs

Scribe Line Marks (SLM) printed on substrates are a standard method used by modern scanners for wafer alignment. Light reflected from the SLM forms a diffraction pattern which is used to determine the exact position of the wafer. The signal strength of the diffraction order needs to reach a certain threshold for the scanner to detect it. The marks are changed as the wafers go through various processes and are buried underneath complex film stacks. These processes and stacks can severely reduce wafer quality (WQ). Equipment manufactures recommend several variations of the SLM to improve WQ but these variations are not effective for certain advanced processes. This paper discusses theoretical analysis of how SLM designs affect wafer quality, addresses the challenge of self-aligned double patterning (SADP) on SLMs and experimentally verifies results using various structures.

Improving aberration control with application specific optimization using computational lithography

As the industry drives to lower k1 imaging we commonly accept the use of higher NA imaging and advanced illumination conditions. The advent of this technology shift has given rise to very exotic pupil spread functions that have some areas of high thermal energy density creating new modeling and control challenges. Modern scanners are equipped with advanced lens manipulators that introduce controlled adjustments of the lens elements to counteract the lens aberrations existing in the system. However, there are some specific non-correctable aberration modes that are detrimental to important structures. In this paper, we introduce a methodology for minimizing the impact of aberrations for specific designs at hand. We employ computational lithography to analyze the design being imaged, and then devise a lens manipulator control scheme aimed at optimizing the aberration level for the specific design. The optimization scheme does not minimize the overall aberration, but directs the aberration control to optimize the imaging performance, such as CD control or process window, for the target design. Through computational lithography, we can identify the aberration modes that are most detrimental to the design, and also correlations between imaging responses of independent aberration modes. Then an optimization algorithm is applied to determine how to use the lens manipulators to drive the aberrations modes to levels that are best for the specified imaging performance metric achievable with the tool. We show an example where this method is applied to an aggressive memory device imaged with an advanced ArF scanner. We demonstrate with both simulation and experimental data that this application specific tool optimization successfully compensated for the thermal induced aberrations dynamically, improving the imaging performance consistently through the lot.

Eliminating the offset between overlay metrology and device patterns using computational metrology target design

Designing metrology targets that mimic process device cell behavior is becoming a common component in overlay process control. For an advanced DRAM process (sub 20 nm node), the extreme illumination methods needed to pattern the critical device features makes it harder to control the aberration induced overlay delta between metrology target and device patterns. To compensate for this delta, a Non-Zero-Offset is applied to the metrology measurement that is based on a manual calibration measurement using CD-SEM Overlay. In this paper, we document how this mismatch can be minimized through the right choice of metrology targets and measurement recipe.