Paul D. Shirley
Micron Technology
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Publication
Featured researches published by Paul D. Shirley.
Proceedings of SPIE | 2010
Ted Taylor; Paul D. Shirley; David Dixon; Shoichiro Yanagi; Eri Makimura
Defectivity control continues to challenge advanced semiconductor manufacturing, especially immersion lithography processes. Immersion exposure tools are sensitive to incoming wafer defects, including top coat voids, surface defects, and other random or systematic anomalies. A single defective wafer could contaminate the exposure tools immersion hood resulting in lengthy and costly repairs. To mitigate this problem, TEL developed an integrated and real-time macro inspection solution to identify defective wafers which could potentially damage immersion exposure tools. The Wafer Intelligent Scanner (WIS) module integrates within the CLEAN TRACKTM LITHIUS ProTM platform without impacting footprint or throughput. By utilizing user defined inspection criteria, wafers can be inspected prior to and after exposure for macro defects. Wafers failing to meet inspection criteria prior to exposure are automatically re-routed to bypass the exposure tool and subsequent process modules.
Archive | 2000
Brian F. Gordon; Paul D. Shirley
Archive | 1997
Paul D. Shirley
Archive | 1997
Salman Akram; Paul D. Shirley; William T. Rericha
Archive | 2006
Craig Hickman; Paul D. Shirley
Archive | 1997
Salman Akram; Paul D. Shirley; William T. Rericha
Archive | 2001
Paul D. Shirley
Archive | 2001
Paul D. Shirley
Archive | 2001
Brian F. Gordon; Paul D. Shirley
Archive | 2006
Paul D. Shirley; Craig Hickman