Andrea Chimenton

Radiation effects on floating-gate memory cells

We have addressed the problem of threshold voltage (V/sub TH/) variation in flash memory cells after heavy-ion irradiation by using specially designed array structures and test instruments. After irradiation, low V/sub TH/ tails appear in V/sub TH/ distributions, growing with ion linear energy transfer (LET) and fluence. In particular, high LET ions, such as iodine used in this paper, can produce a bit flip. Since the existing models cannot account for large charge losses from the floating gate, we propose a new mechanism, based on the excess of positive charge produced by a single ion, temporarily lowering the tunnel oxide barrier (positive charge assisted leakage current) and enhancing the tunneling current. This mechanism fully explains the experimental data we present.

Anomalous charge loss from floating-gate memory cells due to heavy ions irradiation

We are presenting new data on the charge loss in large floating gate (FG) memory arrays subjected to heavy ion irradiation. Existing models for charge loss from charged FG and generation-recombination after a heavy ion strike are insufficient to justify (or in contrast with) our experimental results. In particular, the charge loss is by far larger than predicted by existing models, it depends on the number of generated holes, not on those surviving recombination, and it is larger for FGs with larger threshold voltage before irradiation. We show that these data can be explained as the effect of two different mechanisms. The first one is a semi-permanent multi trap-assisted tunneling (TAT), which closely resembles anomalous stress induced leakage current (SILC) in electrically stressed devices. The second mechanism is a transient phenomenon responsible for the largest part of the lost FG charge. Detailed physical modeling of this mechanism is still not available, owing to the limited knowledge of the physical background under these phenomena, but three possible models are explored and discussed.

Data retention after heavy ion exposure of floating gate memories: analysis and simulation

Floating gate (FG) memories are the most important of current nonvolatile memory technologies. We are investigating the long-term retention issues in advanced Flash memory technologies submitted to heavy ion irradiation. Long tails appear in threshold voltage distribution of cells hit by ions after they have been reprogrammed. This phenomenon is more pronounced in devices with smaller gate area. Results are explained by a new physics-based model of the leakage current flowing through the damaged oxides of FG memory cells. The model calculates the trap-assisted tunneling current through a statistically distributed set of defects by using electron coupling to oxide phonons. The model is used to fit experimental data and to discuss retention properties after heavy ions exposure of future devices, featuring thinner tunnel oxide.

Overerase phenomena: an insight into flash memory reliability

The most important reliability issues related to the erasing operation in flash memories are, still today, caused by single bit failures. In particular, the overerase of tail and fast bits affects the threshold voltage distribution width, causing bit-line leakage that produces read/verify circuitry malfunctions, affects the programming efficiency due to voltage drop, and causes charge-pump circuitry failure. This brief overview explores the most important characteristics of these anomalous bits, their relation with the erratic erase phenomena and their impact on flash memory reliability. Identification techniques, experimental results, and physical models are also discussed.

Analysis of erratic bits in flash memories

This work presents experimental results concerning erratic behaviors in flash memories obtained by tracking the threshold voltage dynamics during any single erase operation and providing a deeper insight into their physical nature. The particular shape of the experimental erase curves allows the derivation of a nearly linear relationship between the amplitude of erratic threshold shifts and the equivalent barrier height controlling Fowler-Nordheim injection.

Call for papers - Wireless Technology: Models, Designs and Applications

This paper presents experimental results and statistics about the erratic erase in Flash Memories, setting the basis for any physical modeling of the phenomena and data comparison. Statistical parameters like the reliability function and the failure rate have been measured and modeled by analytical functions showing that all cells of an array may potentially exhibit erratic events. By mapping the physical position of each erratic bit in a sector and using an equivalent cell approach, it has been possible to establish a correlation between the erratic phenomena and the intrinsic amorphous nature of SiO/sub 2/. Tail bits of the erased distribution have been shown to be caused by erratic events suggesting a unique physical cause for the two phenomena. The relation between positive and negative shifts has also been discussed and overerase risks caused by erratic behaviors have been estimated.

Constant charge erasing scheme for flash memories

This paper presents a new erasing scheme for flash memories based on a sequence of bulk to gate-box pulses with increasing voltage amplitude. It is experimentally and analytically demonstrated that the erasing dynamics always reaches an equilibrium condition where each pulse induces a constant and controllable injected charge and, therefore, constant threshold shifts. The analytical study allows us to express both the final threshold voltage and the oxide electric field as a function of technological, physical, and electrical parameters. Electrical parameters can be conveniently adapted to control both the threshold voltage and the oxide fields, thus reducing oxide stresses. Advantages with respect to the standard box erasing scheme are theoretically and experimentally demonstrated.

Reliability and performance characterization of a mems-based non-volatile switch

In this paper we report data on the reliability and performance characterization of a CMOS-based non-volatile memory (NVM) array, the operating principle of which is based on stiction forces within a MEMS switch. Unlike any other NVM technology, the data retention of this technology improves with increasing temperatures. The switches have been proven to operate over an extremely wide temperature range from −150°C to 300°C, in a 4MRad/s radiation environment and can withstand acceleration forces up to 20,000g. The technology is an ideal candidate for highly reliable non-volatile memory in harsh environmental applications, like auto-motive, defense, space, down-well and geo-thermal. This NVM switch and a tunable RF-MEMS capacitor will be the first products based on this CMOS integrated MEMS platform.

Drain-accelerated degradation of tunnel oxides in Flash memories

A new technique for separating the oxide damage due to program/erase (P/E) cycling and of parasitic hot-hole injection due to bitline biasing in Flash memories is presented. The technique is based on an analysis of the spatial distribution of anomalous tail cells in the array subjected to P/E cycling. We show that electron and hole injection have different dependences on the number of P/E cycles, with the latter becoming the dominating mechanism for large cycling.

A statistical model of erratic erase based on an automated random telegraph signal characterization technique

We propose a new statistical model of the erratic erase based on a new RTS analysis technique. The experimental analysis revealed new interesting features of the erratic erase phenomenon. The overall erased threshold voltage distribution, including tail bits, can be modeled by taking into account the erratic erase behavior whose characteristics can easily be measured by common cycling experiments. The statistical model of the erased threshold voltage obtained in this way can then be used to perform statistical simulation of the bitline leakage current, thus providing a powerful tool in memory design and optimization.