D.B.M. Klaassen

Electroplating of conductive polymers for the metallization of insulators

Abstract Electrodeposition of copper was investigated on thin films of poly(3,4-ethylenedioxythiophene) (PEDOT). This conducting polymer can be processed from solution and exhibits a high specific conductivity of about 300 S/cm. N -(3-Trimethoxysilyl-propyl)pyrrole was applied as a primer in order to adhere PEDOT to the substrates. The lateral propagation or front velocity of the copper front and the uniformity of the copper deposit were determined as a function of sheet resistance of the PEDOT films, type of PEDOT counterions, and of the temperature, applied potential and composition of the electrochemical baths. The experimental data obtained are interpreted using a simple mathematical model to describe transient thickening during electrodeposition on electrodes of high ohmic resistance. A good agreement with experimental data is obtained, especially for the front velocity being inversely proportional to the square root of the sheet resistance. Quantitative analysis of uniformity data shows that the affinity for nucleation is much higher on the conducting polymer than on the deposited metal. This conclusion is supported by activation energies as determined from temperature-dependent metallization experiments. Finally, adhesion of copper deposits as a function of copper thickness and morphology of the substrate are discussed.

Record RF performance of standard 90 nm CMOS technology

We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.

DEGRADATION OF PHOSPHORS UNDER CATHODE-RAY EXCITATION

Received 2 September 1986 Revised 16 December 1986 Accepted 7 January 1987 A systematic analysis of phosphor degradation is presented. An increase of the self-absorption of the luminescence, destruction of luminescence centres, a decreased energy flow to these centres, and increased energy losses in the phosphor host lattice - both in the bulk and at the surface - can be distinguished as causes of the deterioration of the external radiant efficiency of phosphors. Simple measurements are suggested to disentangle the contribution of each of these parameters to the observed degradation effects. As an illustration degradation effects of Zn,SiO, : Mn, Y2SiOs : Ce, Sr,Al,O,,

Capacitance modeling of laterally non-uniform MOS devices

In compact transistor modeling for circuit simulation, the capacitances of conventional MOS devices are commonly determined as the derivatives of terminal charges, which on their turn are obtained from the so-called Ward-Dutton charge partitioning scheme (Ward, 1981). For devices with a laterally non-uniform channel doping profile, however, it is shown in this paper that: 1) no terminal charges exist for the description of capacitances. Instead, 2) a model is presented for the capacitances of such devices, including numerical results for a MOS transistor with a laterally diffused channel doping profile. Finally, 3) a method is given to incorporate such a capacitance model in circuit simulators which are traditionally based on terminal charge models.

New compact model for induced gate current noise [MOSFET]

Accurate compact modeling of induced gate noise is a prerequisite for RF CMOS circuit design. Existing models underestimate the induced gate noise for short-channel devices. In this paper, a new model is introduced, based on an improved Klaassen-Prins approach, which accurately accounts for velocity saturation. The model accurately describes noise without fitting any additional parameters.

Compact modeling of noise in CMOS

The physical background of the thermal noise equations of the PSP MOSFET model is presented. The PSP thermal noise model is shown to pass a number of proposed benchmark tests for MOSFET thermal noise. Without any fitting parameters, it is shown to predict with great accuracy a collection of experimental data on three modern CMOS technologies. The impact of device layout on noise properties is discussed and demonstrated experimentally

A new compact model for junctions in advanced CMOS technologies

We present a new compact model for the junction capacitances and leakage currents in deep-submicron CMOS technologies. The model contains Shockley-Read-Hall generation/recombination, trap-assisted tunneling, band-to-band-tunneling, and avalanche breakdown. It has been validated for a wide range of bias and temperature, for NMOS and PMOS junctions, and for different CMOS generations

The RF Potential of High-performance 100nm CMOS Technology

We have investigated the RF potential of 100nm CMOS technology. A high cut-off frequency of 140 GHz for 80nm (actual gate length) NMOS devices was achieved. Combining on wafer measurements with the compact model MOS model 11, we demonstrate that an fmax of 320GHz is achievable on scaled NMOS devices.

Compact MOS Modelling for RF CMOS Circuit Simulation

Modem CMOS technologies are becoming increasingly attractive for RF applications.This imposes stringent requirements on compact models used in circuit simulation: not only currents and charges, but also noise, power gain, impedances, and harmonic distortion must be modelled accurately. In this paper several of these issues will be addressed with the help of Philips’ new public-domain compact MOS model, MOS Model 11.

RF CMOS Modelling

RF application of CMOS requires accurate modelling of transistor properties, such as impedance levels, power gain, noise, distortion, substrate parasitics and nonquasi-static effects. Apart from noise, until now relative little attention has been paid to these properties in compact models for circuit simulation. Here clear experimental results will be used to illustrate the accuracy and limitations of state-of-the-art compact models. Wherever possible, improvements or macro models that can be used for circuit simulation will be presented.