R. van Langevelde

Noise modeling for RF CMOS circuit simulation

The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation

This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context

RF-CMOS performance trends

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1/f noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.

Accurate thermal noise model for deep-submicron CMOS

Extensive measurements of drain current thermal noise are presented for 3 different CMOS technologies and for gate lengths ranging from 2 /spl mu/m down to 0.17 /spl mu/m. Using a surface-potential-based compact MOS model with improved descriptions of carrier mobility and velocity saturation, all the experimental results can be described accurately without invoking carrier heating effects or introducing additional parameters.

RF-distortion in deep-submicron CMOS technologies

The distortion behaviour of MOSFETs is important for RF-applications. In this paper the influence of technology variations (oxide thickness, substrate doping,...) on distortion is investigated using measurements and a recently developed compact MOSFET model. The influence on distortion of technology scaling down to 0.18 /spl mu/m is verified and further scaling according to the ITRS-roadmap is predicted.

An ultra-low-power 868/915 MHz RF transceiver for wireless sensor network applications

This paper describes an ultra-low-power RF transceiver implemented as part of a system-on-chip. The transceiver operates in the 868/915 MHz frequency band using binary FSK modulation at a 45 kbit/s data rate. It achieves −89 dBm receiver sensitivity and −6 dBm transmitter output power while consuming 1.6 mA and 1.8 mA, respectively, from a 1.2 to 1.5 V supply. It is fabricated in 0.13 µm CMOS occupying 1.5 mm2, and it uses only four external components (i.e., battery, antenna, SAW-filter and crystal). The transceiver offers a small form factor, low cost and low power solution for wireless sensor network applications.

Generalizations of the Klaassen-Prins equation for calculating the noise of semiconductor devices

The Klaassen-Prins equation is the standard equation for calculating the drain thermal noise of long-channel MOSFETs. We show that the Klaassen-Prins equation is not always valid, even for MOSFETs. We present generalizations to the Klaassen-Prins equation that include velocity saturation effects of short-channel MOSFETs and that comprise also induced gate noise.

Gate current: Modeling, /spl Delta/L extraction and impact on RF performance

In this paper a new physical gate leakage model is introduced, which is both accurate and simple. It only uses 5 parameters, making parameter extraction straightforward. As a result the model can be used to extract effective length for modern CMOS technologies. The influence of gate current on the RF performance is studied.

RF-CMOS Performance Trends

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1 noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.

Record RF performance of standard 90 nm CMOS technology

We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.