R.J. Havens

Noise modeling for RF CMOS circuit simulation

The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

Accurate thermal noise model for deep-submicron CMOS

Extensive measurements of drain current thermal noise are presented for 3 different CMOS technologies and for gate lengths ranging from 2 /spl mu/m down to 0.17 /spl mu/m. Using a surface-potential-based compact MOS model with improved descriptions of carrier mobility and velocity saturation, all the experimental results can be described accurately without invoking carrier heating effects or introducing additional parameters.

RF capacitance-voltage characterization of MOSFETs with high leakage dielectrics

We present a MOS Capacitance-Voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.

RF-distortion in deep-submicron CMOS technologies

The distortion behaviour of MOSFETs is important for RF-applications. In this paper the influence of technology variations (oxide thickness, substrate doping,...) on distortion is investigated using measurements and a recently developed compact MOSFET model. The influence on distortion of technology scaling down to 0.18 /spl mu/m is verified and further scaling according to the ITRS-roadmap is predicted.

Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes

In this paper, we provide an extensive experimental and theoretical study of the benefits of patterned ground shield interconnect transmission lines over more conventional layouts in advanced integrated-circuit processes. As part of this experimental work, we present the first comparative study taken on truly differential transmission line test structures. Our experimental results obtained on transmission lines with patterned ground shields are compared against a predictive compact equivalent-circuit model. This model employs exact closed-form expressions for the inductances, and describes key performance figures such as characteristic impedance and attenuation loss with excellent accuracy

Predictive spiral inductor compact model for frequency and time domain

A highly accurate predictive inductor model for integrated symmetric inductors with center tap and patterned ground shield is presented. This model is based on a modified Greenhouse algorithm where current crowding due to skin and proximity effects is included by considering the spread in parallel sub-loop inductances. This scalable symmetrical inductor equivalent circuit model covers all operating conditions, and yet only requires dimensions and back-end layer thicknesses. We have verified this scalable model for a large number of inductors from three industrial IC processes and found excellent agreement with measured inductances, Q-factors, and resonance frequencies.

Record RF performance of standard 90 nm CMOS technology

We have optimized 3 key RF devices realized in standard logic 90 nm CMOS technology and report a record performance in terms of n-MOS maximum oscillation frequency f/sub max/ (280 GHz), varactor tuning range and varactor and inductor quality factor.

Physics-based wideband predictive compact model for inductors with high amounts of dummy metal fill

A computationally efficient physics-based wideband predictive inductor compact model is presented that is capable of evaluating the impact on inductance and quality factor of dummy metal fill-cells. In a modern integrated-circuit process, high amounts of these fill-cells are required to meet metal density rules and guarantee adjacent circuit integrity. The predictions made with this model are shown to be in agreement with data measured on symmetrical octagonal inductors realized in a 90-nm CMOS process with varying amounts of dummy metal fill-cells. We further provide all inductance equations, list additional sources of eddy current losses, and discuss layout modifications, which would further improve the performance of the integrated inductors

Compact modeling of drain and gate current noise for RF CMOS

A model for RF CMOS circuit design is presented that is capable of predicting drain and gate current noise without adjusting any parameters. Additionally, the presence of (i) noise associated with avalanche multiplication, and (ii) shot noise of the direct-tunneling gate current in leaky dielectrics is revealed.

Test structure design considerations for RF-CV measurements on leaky dielectrics

We present an MOS capacitance-voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.