D.C. La Tulipe

Three-dimensional integrated circuits

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 108 vias/cm2), and extremely aggressive wafer-to-wafer alignment (submicron) capability.

Wafer-level 3D integration technology

An overview of wafer-level three-dimensional (3D)) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.

Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)

We present solutions to the key process technology challenges of three-dimensional (3D) integrated circuits (ICs) that enable creation of stacked device layers with the shortest distance between them, the highest interconnection density and extremely aggressive wafer-to-wafer alignment. To achieve this important 3D IC technology milestone, we optimized the layer transfer process to include a glass handle wafer, oxide fusion bonding, wafer bow compensation methods, and a single damascene patterning and metallization method for creation of high-aspect-ratio (6:1 < AR < 11:1) contacts between two stacked device layers

Process optimization for high electron mobility in nMOSFETs with aggressively scaled HfO/sub 2//metal stacks

The performance of aggressively scaled (1.4nm<T/sub inv/<2.1nm) self-aligned HfO/sub 2/-based nMOSFETs with various metal gate electrodes (W, TaN, TiN, and TaSiN) is optimized. It is shown that high mobility values, competitive with oxynitride controls (SiON/poly-Si, T/sub inv//spl sim/1.8-2.1nm), can be achieved. Detailed studies of the role of interface states, remote charges in the HfO/sub 2/ layer, interfacial layer regrowth, and nitrogen-induced charge lead to the conclusion that high-temperature-induced structural modifications near the SiO/sub 2//HfO/sub 2/ interface substantially improve the electron mobility.

Positive mode silylation process characterization

Abstract In this paper we wish to report on our progress in developing a positive TSI system with emphasis on what we believe is a novel approach for characterizing the silylation process.

Thermally stable ohmic contacts to n‐type GaAs. VIII. Sputter‐deposited InAs contacts

The electrical properties and microstructure of InAs ohmic contacts to n‐type GaAs, prepared by sputter‐depositing a single target, were studied by measuring the contact resistance (Rc) by the transmission line method and analyzing the interfacial structure by x‐ray diffraction and cross‐sectional transmission electron microscopy. Current‐voltage measurement of an as‐deposited InAs/W contact showed Schottky behavior, where the W layer was used as a cap layer. The InAs layer had an amorphous structure and a uniform oxide layer was observed at the InAs/GaAs interface. Even after annealing at 800 °C, ohmic behavior was not obtained in this contact because the intervening oxide layer prevented the InAs and GaAs interaction. By adding Ni to the InAs/W contacts (where Ni was deposited by an evaporation method), the interaction between the InAs and the GaAs was enhanced. Nickel interacted with As in the InAs layer and formed NiAs phases after annealing at temperature above 600 °C. The excess In in the InAs layer...

Excess Gate Current Due to Hot Electrons in GaAs-Gate FETs

We report on the first observations of hot electron effects in the gate current of GaAs-gate FET’s. We have made and tested a variety of these FET’s using MBE-grown material with 60nm and 35nm thick Al.4Ga.6As gate insulator layers. In measurements at 300K and 77K these devices show drain-voltage-dependent gate current substantially exceeding that which would be expected on the basis of simple vertical transport measurements. We attribute this current to the real-space transfer of hot electrons from the channel of the device into the (Al,Ga)As/GaAs barrier, from which they are collected into the gate.

Low Energy Electron Beam Top Surface Image Processing Using Chemically Amplified AXT Resist

High resolution processes are demonstrated with a positive-mode chemically amplified AXT top surface imaging resist system exposed with a low energy electron beam. Top surface imaging is an ideal match to low energy electron beam lithography because it allows thick resist layers to be patterned despite the limited penetration depth of the electron beam. The three key steps of the process are exposure, silylation, and etch development. All three steps influence the final process sensitivity, contrast, and resolution. The AXT has a poly(hydroxy styrene) base resin, and has been formulated both with and without a dye used to enhance optical absorption. We have achieved sub 100 nm resolution both with and without a postexposure bake. Critical area doses below 1 μC/m2 are demonstrated. The edge roughness and density of etch residue from silylation defects have been compared for a variety of oxygen plasma etch systems.

Novel InAs/(Al,Ga)Sb FET with direct gate-to-channel contact

A new type of FET has been fabricated in which the gate is in direct contact with the channel. There is no intervening charge separating layer. Instead, the separation of gate and channel carriers is achieved by using the staggered band alignment of InAs/(Al,Ga)Sb such that a p/sup +/ (Al,Ga)Sb gate layer is placed in direct contact with the n-type InAs channel. At 77 K the measured devices show both current gain and voltage gain, and a maximum transconductance of 500 mS/mm has been observed.<<ETX>>

Depletion-mode GaAs SISFET's by selective ion implantation

Silicon donors have been implanted through the gate and into the (Al,Ga)As insulator of a GaAs SISFET structure in order to produce a negative shift in the device threshold voltage in selective areas of the wafer. The depletion-mode devices fabricated in this manner have controllable threshold voltage, high transconductance (350 mS/mm at 300 K and 380 mS/mm at 77 K for 1-µm gate-length devices), and low gate leakage characteristics. Such devices are suitable for enhance-deplete GaAs SISFET logic circuits.