D. Corso

Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)

In this paper, an overview of todays status and progress, as well as tomorrows challenges and trends, in the field of advanced nonvolatile memories based on discrete traps is given. In particular, unique features of silicon nanocrystal and SONOS memories will be illustrated through original recent data. The main potentials and main issues of these technologies as candidates to push further the scaling limits of conventional floating-gate Flash devices will be evaluated.

How far will silicon nanocrystals push the scaling limits of NVMs technologies

For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.

Dark Current in Silicon Photomultiplier Pixels: Data and Model

The dark current behavior of the pixels forming the Si photomultiplier as a function of the applied overvoltage and operation temperature is studied. The data are modeled by assuming that dark current is caused by current pulses triggered by events of diffusion of single minority carriers injected from the peripheral boundaries of the active area depletion layer and by thermal emission of carriers from Shockley–Read–Hall defects in the active area depletion layer.

Peculiar aspects of nanocrystal memory cells: data and extrapolations

Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigated. The cell can be also programmed by channel hot electron injection, allowing the possibility to multibit storage. The suppression of the drain turn-on and the possibility of using this cell for multibit storage give us a clear evidence of the distributed nature of the charge storage.

Radiation Tolerance of NROM Embedded Products

Radiation tolerance of NROM memories is demonstrated at the level of industrial 4 Mbit memory embedded modules, specifically not designed for operation in radiation harsh environments. The memory fabricated in 0.18 um technology remains fully functional after total ionization doses exceeding 100 krad. The tests were performed by irradiating with γ-rays ( 60Co source) and 10 MeV 11B ions in active (during programming/erase and read-out) and passive (no bias) modes. Comprehensive statistics were obtained by using large memory arrays and comparison of the data with the parameters of irradiated single cells allowed deep understanding of the physical phenomena in the irradiated NROM devices for both moderate (<;1 Mrad) and large (> 1 Mrad) TID. The obtained data is currently employed in the design of the new generation of NROM memories, having improved radiation tolerance.

Advantages of the FinFET architecture in SONOS and Nanocrystal memory devices

Double-gate and tri-gate FinFET type memories with nitride (SONOS-like) or Si nanocrystals storage with minimum feature sizes of 10 nm were realized. Strong performance advantages in program / erase characteristics and reliability deeply linked to the FinFET architecture are demonstrated.

Optimized silicon photomultipliers with optical trenches

This paper reports on the electrical characteristics of silicon photomultipliers (SiPM) with optimized optical trench technology. The SiPM arrays were characterized from single pixels up to the full 64×64 pixel device. The data clearly show a perfect scaling of the dark current with the pixel number, thus indicating an almost ideal insulation among the pixels in the whole voltage operating range.

Ionizing Radiation Effects on Non Volatile Read Only Memory Cells

Threshold voltage (<i>V</i>_th) and drain-source current (<i>I</i>_DS) behaviour of nitride read only memories (NROM) were studied both in situ during irradiation or after irradiation with photons and ions. <i>V</i>_th loss fluctuations are well explained by the same Weibull statistics regardless of the irradiation species and total dose. Results of drain current measurements in-situ during irradiation with photons and ions reveal a step-like increase of <i>I</i>_DS with the total irradiation dose. A brief physical explanation is also provided.

Localized charge storage in nanocrystal memories: feasibility of a multi-bit cell

We have realized Si nanocrystal memory cells in which the Si dots have been deposited by chemical vapor deposition (CVD) on the tunnel oxide and then covered by a CVD control oxide. In this paper we report a study on the potential of this type of cell for multi-bit storage. In particular, the possibilities offered by these devices from the point of view of program/erase mechanisms, endurance, and charge retention are shown and discussed.

Memory effects in MOS devices based on Si quantum dots

Abstract Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO2 between the grains, the lateral charge loss is reduced and, thus, long retention time are possible. In this work we present good memory action characterised by low write voltages, write times of the order of milliseconds and long retention time in spite of the low tunnel oxide thickness.