D. De Roest

Global interconnect trade-off for technology over memory modules to application level: case study

In this paper we show how to exploit energy-delay trade-offs that exist due to the variation of the technology parameters for the implementation of interconnect wires. We also evaluate how these trade-offs can be propagated to the memory module level, so we can minimise the power consumption of the entire memory organisation (i.e., memories and connections between them). Our approach is that at future technology nodes the delay problem can be handled at the application level, so given any delay slack obtained at that level, we can exploit it to make the switching on the interconnect wires slower and thus less energy consuming. In this way, we have shown that for real-life applications the power consumption at future technology nodes can be reduced by about 34%, when compared to the option provided by the ITRS roadmap. This is achieved by, instead of using the very fast and power hungry wires, selectively using slower and thinner interconnect wires while still meeting the application real-time constraints.

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

We demonstrate a NMOS Si Bulk-FinFET with extension doped by Phosphorus doped Silicate Glass (PSG). Highly doped PSG (6e21 cm^-3) was used as a diffusion source. SiO₂ cap on PSG decreased sheet resistance (Rs) due to less out diffusion of P. Even when thin SiO₂ exists at the interface between Si and PSG, P diffused from PSG into Si. Thanks to the high etch rate of the PSG/SiO₂ cap stack after drive-in anneal, the PSG/SiO₂ cap was successfully removed by HF with minimum removal of STI and gate hard mask oxide. PSG provides damage free and uniform sidewall doping to fin. On current I_ON is improved by 20% for L_G in the 30-24 nm range, with similar I_OFF and better DIBL compared to P ion implanted reference.

Quantifying LER to predict its impact on BEOL TDDB reliability at 20nm ½ pitch

We present results of a refined model that allows prediction of the influence of LER on the TDDB performance when scaling towards 20nm ½ pitch. The model is validated on 35nm ½ pitch state-of-the-art Cu/low-k interconnects, defined in a double patterning integration scheme, using wafer-level TDDB measurements and in-line post-CMP evaluation of both low-k space and parameters describing LER. The results predict a 9 orders of magnitude reduction in TDDB lifetime at 20nm ½ pitch in case uncor-related LER is not scaling, but no further degradation due to protrusions in the dielectric space.

New modeling approach of on‐chip interconnects for RF integrated circuits in CMOS technology

New analytical approximation for the frequency‐dependent impedance matrix components of symmetric VLSI interconnect on lossy silicon substrate are derived. The results have been obtained by using an approximate quasi‐magnetostatic analysis of symmetric coupled microstrip on‐chip interconnects on silicon. We assume that the magnetostatic field meets the boundary conditions of a single isolated infinite line; therefore, the boundary conditions for the conductors in the structure are approximately satisfied. The derivation is based on the approximate solution of quasi‐magnetostatic equations in the structure (dielectric and silicon semi‐space), and takes into account the substrate skin‐effect. Comparisons with published data from circuit modeling or full‐wave numerical analyses are presented to validate the inductance and resistance expressions derived for symmetric coupled VLSI interconnects. The analytical characterization presented in this paper is well situated for inclusion into CAD codes in the design of RF and mixed‐signal integrated circuits on silicon.

Key factors to sustain the extension of a MHM-based integration scheme to medium and high porosity PECVD low-k materials

Interconnect solutions for advanced technology nodes using PECVD techniques for low-k deposition require the use of porogen-based process with post deposition UV cure. By using two different UV cure lamps (A, B) in combination with different porogen loads, three different micro-porous low-k films are developed: Aurora® ELK HM (k~2.5; porosity (P) ~25%), Aurora® ELK A (k~2.3; P~34%) and Aurora® ELK B (k~2.2; P~37%). Integrating these materials is complex and challenging. We discuss key factors that are instrumental to the extension of a metal hard mask (MHM)-based integration scheme to these 3 low-k films. Our findings: (I) for sub-100nm dimensions, patterning and low-k interactions affect the dynamic of organic residue formation and thereby impact electrical yield; (II) choosing the right ash, etch and clean sequence is mandatory to control plasma damage, profile, residues and corrosion on top of the MHM; (III) Cu reduction plasmas must be adjusted when porosity is increased to mitigate field damage.

Interconnect exploration for future wire dominated technologies

Storage takes the centre stage [4] in more and more information oriented systems because of the eternal push for more complex applications with especially larger and more complicated data types. In addition, the access speed, size and power consumption associated with this storage form a severe bottle-neck in these systems (especially in an embedded context). In this invited paper, we want to explore the interconnect related issues, both inside the storage components (intra-memory) and between the components (inter-memory). To achieve this we have performed several experiments with a storage organisation exploration tool set that has been applied to a real-life application from our target domain, namely a Digital Audio Broadcast (DAB) receiver. Several interesting conclusions can be based on these experiments and these will be briefly summarised below.

Critical issues in the integration of copper and low-k dielectrics

Single and dual damascene Cu/low k processes are evaluated. Critical integration issues are discussed. Good Cu continuity is obtained over long meanders. The via resistance in dual damascene structures is optimized and the values obtained are almost three times lower than those achieved for a conventional Al/W metallization process. The interline capacitance was evaluated for various etch and strip procedures. The effect of the Cu/low k process on a front end of line 0.25 /spl mu/m n-MOS process is investigated. The metallization process does not affect the performance of either transistors or field transistors.

Physical and electrical characterization of silsesquioxane-based ultra-low k dielectric films

Physical and electrical characterization of a Dow Corning silsesquioxane-based ultra-low k dielectric is presented. The film properties, such as refractive index, SiH bond density, thermal stability and susceptibility to moisture absorption are investigated as a function of processing conditions. It is shown that exposure of the films to plasma environments results in a change of porosity. A low-K dielectric film with a pore size around 3.5 nm is successfully integrated in 0.2 /spl mu/m single damascene structures.

Highly accurate closed form approximation for frequency-dependent line impedance of a lossy Silicon substrate IC interconnect

A new analytic model is presented to calculate the frequency-dependent distributed self and mutual inductance and the associated distributed series resistance of silicon semiconducting IC interconnects. The method is based on the induced current density distribution inside silicon substrate. The validity of the proposed model has been checked by a comparison with a quasi-TEM spectral domain approach and equivalent-circuit modeling procedure. It is found that the silicon semiconducting substrate skin effect must be considered for the accurate prediction of the high-frequency characteristics of IC interconnects.