N. Revil

A thorough investigation of MOSFETs NBTI degradation

An overview of evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented. The physical mechanisms of the degradation as well as the different defects involved have been discussed according to a systematic set of experiments with different stress conditions. According to our findings, a physical model is proposed which could be used to more accurately predict the transistor degradation. Finally, the influence of different process splits as the gate oxide nitridation, the nitrogen content, the source/drain implant and poly doping level on the NBTI degradation is investigated and discussed with our present understanding.

0.13

This paper presents a complete 0.13 μm SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 fF/μm2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models.

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This paper gives an insight into the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. negative bias temperature instability (NBTI) and positive bias temperature instability in both NMOS and PMOS have been compared and a possible explanation for all configurations has been suggested. Recovery and temperature effect under NBTI were also investigated showing different behaviors of the two components.

m SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications

A study of the electric field dependence of the TDDB activation energy is presented for 12 nm down to 4.7 nm thin oxides. It is shown that the TDDB activation energy depends linearly on the stress electric field and that this behavior depends strongly on the oxide thickness. Moreover, a relationship between the TDDB activation energy attenuation per WV/cm and the oxide thickness has been found. As will be demonstrated, these results are of great importance for the rigorous estimation of the oxide lifetime of both present and future technologies.

Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide

The decrease of the threshold voltage Vth of hole channel metal–oxide–semiconductor field effect transistors with ultrathin gate dielectric layers under negative bias temperature stress is studied. A degradation model is developed that accounts for the generation of Si3≡Si• (Pb0) centers and bulk oxide defects, induced by the tunneling of electrons or holes through the gate dielectric layer during electrical stress. The model predicts that Vth shifts are mainly due to the tunneling of holes at low gate bias |VG|, typically below 1.5 V, while electrons are mainly responsible for these shifts at higher |VG|. Consequently, device lifetime at operating voltage, based on Vth shifts, should not be extrapolated from measurements performed at high gate bias. The impact of nitrogen incorporated at the Si/dielectric interface on Vth shifts is investigated next. The acceleration of device degradation when the amount of nitrogen increases is attributed to the increase in local interfacial strain, induced by the incre...

Electric field dependence of TDDB activation energy in ultrathin oxides

The transistor performances and hot-carrier reliability in n-MOSFETs are investigated at high temperature in the range 25‐125 8C. A careful analysis of the temperature dependence of the device parameters shows that transistor performances are significantly reduced and that the Fermi potential, the mobility and current reductions, contribute to decrease the device sensitivity to the hot-carrier damage at high temperature. DiAerent degradation behaviors are found between DC and AC stressing depending on the degradation mechanisms i.e. whether the interface trap generation or oxide charge trapping dominates which consequently exhibits a strong temperature dependence through their magnitude and localization. It is pointed out that the reduction of the ionization rate significantly impacts the degradation behaviors at elevated temperature. Even if the amount of generated damage is slightly larger than what eAectively influences the transistor characteristics, the parameter insensitivity to given at high temperature improves the transistor reliability. This improvement is determined in the value of the device lifetime at 125 and 70 8C using inverter and pass transistor operations in a 0.35 mm LDD complementary metal-oxide semiconductor (CMOS) technology suitable for 3.3 V operation. # 1999 Elsevier Science Ltd. All rights reserved.

Modeling negative bias temperature instabilities in hole channel metal-oxide-semiconductor field effect transistors with ultrathin gate oxide layers

We have investigated the degradation behavior of single transistors using DC and AC alternating stress conditions as the interface trap generation and the charge trapping/detrapping phenomena become a competitive interaction during AC cycles in 0.25 /spl mu/m CMOS technologies with 5 nm thick gate-oxide. In this way, we determine to what extent the effects and mechanisms are affecting the resultant degradation behavior between N- and P-MOSFETs in order to explain the degradation observed in actual circuits. The effect of temperature is further investigated between -40/spl deg/C and 125/spl deg/C as Negative Bias Temperature Instability (NBTI), thermal emission, field-enhanced charge detrapping may contribute to the transistor degradation and modify the circuit degradation. We verify the usefulness of the experimental procedure and model based on duty cycle calculations for ring oscillators.

Analysis of high temperature effects on performances and hot-carrier degradation in DC/AC stressed 0.35 μm n-MOSFETs

We focus in this study on the negative bias temperature instability (NBTI)-induced /spl Delta/N/sub IT/ phenomenon and we point out its relative gate-oxide thickness (T/sub OX/) dependences. Studies are carried out in a large T/sub OX/ range, comparing the gate-oxide quality which was grown with or without nitrogen incorporation. We have developed an oxide field (F/sub OX/) dependence for /spl Delta/N/sub IT/ and we show the two opposite effects of T/sub OX/ on the threshold voltage shift (/spl Delta/V/sub T/). Simulation of both effects shows a good correlation with experimental results in pure oxide and confirms the reduced interface trapped charge effect in /spl Delta/V/sub T/ in nitrided devices. Results enable us to extrapolate the NBTI impact when T/sub OX/ is varied which allows us to determine in a useful way the security margin during the gate-oxide process optimization.

Hot-carrier damage in AC-stressed deep submicrometer CMOS technologies

Abstract Hot-carrier reliability is studied in core logic PMOSFETs with a thin gate-oxide (Tox=2 nm) and in Input/Output PMOSFETs with a thick gate-oxide (6.5 nm) used for systems on chip applications. Hot-hole (HH) injections are found to play a more important role in the injection mechanisms and in the degradation efficiency. This depends on the technology node for stressing voltage conditions corresponding to channel hot-hole injections, i.e. closer to the supply voltage than the other voltage condition. Distinct mechanisms of carrier injections and hot-carrier degradation are found in core devices used for high speed (HS) and low leakage (LL) applications where the hole tunneling current dominates at low voltages while the electron valence band tunneling from the gate occurs at gate-voltages above −1.8 V. Devices with Tox=6.5 nm have shown the existence of a thermionic hot-hole gate-current which is directly measured at larger voltages. This is related to the increase in the surface doping, the thinning of the drain junction depth and the location of the hot-carrier generation rate which is closer to the interface. Results show that hole injections worsen the hot-carrier damage in thin and thick gate-oxides which are both distinguished by the effects of the interface trap generation, the permanent hole trapping and the hole charging–discharging from slow traps using alternated stressing in thin gate-oxides. This consequently leads to a significant lifetime increase in 2 nm HS, LL devices with respect to 6.5 nm Input/Output devices explained by the dominant effect of the fast interface trap generation due to the hole discharge from slow traps and bulk oxide traps in 2 nm devices at the tunneling distance of the interface.

Oxide field dependence of interface trap generation during negative bias temperature instability in PMOS

Negative bias temperature instability (NBTI) in p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with ultrathin oxynitride layers is investigated. The degradation of the threshold voltage and the drain current of the devices arc more important when the nitrogen content at the Si/SiON interface it higher. A degradation model is developed, based on the generation of Si 3 ≡Si . (P b 0 ) centers during electrical stress. The model includes a Gaussian spread of dissociation energies of the P b 0 centers that is closely related to the interfacial strain at the Si/SiON interface. Comparison between the experimental results and the model suggests that the strain at the Si/SiON interface increases when the nitrogen content is higher, leading to a faster degradation of the electrical properties of the devices.