Jean-Luc Ogier

Influence of various process steps on the reliability of PMOSFETs submitted to negative bias temperature instabilities

Abstract In this paper, we analyze the impact of various process steps on the reliability of PMOSFET’s submitted to Negative Bias Temperature Instabilities stress conditions. We give some evidence of the complete thermal anneal of interface states induced by NBTI and investigate the influence of the oxide thickness and of the final forming gas anneal. Then we show a NBTI lifetime improvement after a fluorine implant through the gate and an arsenic bulk doping value increase.

Geometry effects on the NBTI degradation of PMOS transistors

This paper presents the real impact of transistor geometry on the NBTI degradation. IDsat degrades faster longer transistors, which is attributed to the small relative saturation region with respect to the total channel length. Narrow transistor degradation is accelerated by the contribution of the edge of the active region. Transistor lifetime depends on their width in a logarithmic way. It also explain the instability observed in measurements on small area transistors by the impact of very few defects relaxation during the measurements. Low voltage P-channel MOSFETs with various channel lengths and widths are used in this study. According to this work, the worst case for NBTI degradation would be a narrow and long transistor.

Oxide reliability below 3 nm for advanced CMOS: Issues, characterization, and solutions

This tutorial is devoted to oxide reliability below 3 nm in advanced CMOS devices. Indeed, with device dimension downscaling, the oxide thickness reduction below 6 nm has led to important changes in degradation mechanisms and failure modes and this trend has been enhanced below 3 nm. The topics addressed will cover basic aspects, from ITRS predictions to a clear definition of various oxide breakdown events and failure modes and will detail the changes linked to thickness reduction below 3 nm, essentially due to the increasing importance of direct tunneling current through the oxide. Experimental aspects will be highlighted and the statistical treatment using Weibull statistics will be detailed. On the basis of well established experimental points, we will review models for temperature, oxide thickness and voltage dependence of time to breakdown, and will point out the influence of some process factors. In conclusion, we will give some elements concerning the usability of devices and circuits after breakdown.

A new method to quantify retention-failed cells of an EEPROM CAST

The cell array stress test (CAST) is a very simple tool to study one of the main issues of Non Volatile Memory reliability: data retention. However, it is not possible to easily quantify and localise the retention-failed cells of a CAST. Thus, a new experimental technique to localize and to quantify retention-failed EEPROM cells into a CAST is presented in this paper. This new technique is based on light emission microscopy; the aim is to observe light emission coming from cells and to localize their position with accuracy on CAST area. It is a visual and non destructive method which validity has been shown on cycled cells after a retention test.

Energy consumption optimization in nonvolatile silicon nanocrystal memories

In this paper we investigate the energy consumption of Discrete-Trap Silicon Nanocrystal (Si-nc) Nonvolatile Memory Cell during Channel Hot Electron programming operation. We compare this cell with a Floating Gate Flash in order to evaluate the current absorption and the energy consumption under different conditions. Using a commercial TCAD simulator, a good agreement between data and simulations is obtained and the involved mechanisms are analysed. Then we propose a solution to optimize the programming window and energy consumption trade-off for Si-nc Flash Cells.

Total Recovery of Defects Generated by Negative Bias Temperature Instability (NBTI)

NBTI degradation is known to generate defects which can partially recover during a fast interruption. This paper investigates the hole de-trapping effect but also re-trapping kinetics and re-passivation of interface states. The comparison of relaxation at low and high temperatures allows us to conclude that the annealing at 300degC is a real recovery and healing of oxide defects. Indeed, interface states are totally re-passivated and hole traps are de-trapped but have also totally recovered. Furthermore, we show that the retrapping time of oxide traps is three times longer than their generation whatever the stress conditions and relaxation times.

Gate Voltage Matching Investigation for Low-Power Analog Applications

On CMOS technology, some process steps can create a parasitic phenomenon named “hump effect.” This parasitic effect can have a strong impact on gate voltage matching of differential pairs and, as a consequence, on analog circuit performances. In this context, several solutions to limit or remove this hump effect are proposed and described. Silicon data obtained at package and wafer levels for different temperatures are analyzed.

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress

Device degradation modelling is more and more important for reliable circuit design. On MOSFET, the threshold voltage drift in time can lead to circuit performance degradation. In this study, VT shift due to Hot Carrier Injection stress is accelerated on small width devices. VT matching is also degraded during stress as a function of VT deterioration. This width dependence allows explaining gate voltage matching behavior in the sub-threshold area used in low power analog applications.

Microscopic Analysis of Erase-Induced Degradation in 40 nm NOR Flash Technology

An in-depth investigation of NOR flash degradation occurring during Fowler-Nordheim (FN) erase operation is provided. After showing how to properly reproduce the flash equivalent stress on transistors, a complete set of delay-free experiments is performed on MOSFET devices. This paper explores FN-induced SiO2 damage from the two oxide interfaces, capturing both electrostatic aging, by reading the drifts of linear characteristics on single MOSFET, and erase efficiency degradation of the memory cell, by measuring the gate current evolution directly on array structures. After showing how to read the signatures of different defects, important insights are given on physical degradation mechanisms and significant guidelines are provided for the extraction of relevant physical-based parameters for modeling and optimization of flash cell endurance. In particular, the power law correlation between injected and trapped charges has been observed for both types of carriers, highlighting the difference in the power exponent which leads to a turnaround of Vth at erase state during flash endurance. It has been underlined how the holes are mainly trapped close to Si/SiO2 interface, essentially influencing the electrostatics, whereas the electrons are mainly located close to poly/SiO2 interface, mostly impacting the gate current. In addition, an accurate noise-free extraction of electrostatic parameters related to holes and amphoteric defects has been performed highlighting the negligible shift of the total threshold voltage. Finally, the interface trap aging kinetics has been experimentally addressed, emphasizing the weak electron-energy dependence.

Effect of AC stress on oxide TDDB and trapped charge in interface states

This study is driven by the need to improve the oxide reliability of a memory cell. The effects of dynamic high electric field stressing on thin oxide have been studied. Difference between time to breakdown with static stress and dynamic stress has been shown. Trapped charge in interface states under dynamic and static oxide field stress has been investigated with quasi-static capacitance voltage measurement. The duty cycle of the dynamic stress has an important effect on the oxide lifetime. This duty cycle effect is also impacted by the electric field. Interface Hydrogen Released model have been studied to understand relaxation phenomena. Real use stress conditions show an important gain on lifetime.