D. Horelick

A simple diode model including conductivity modulation

A simple lumped component diode model is presented including a representation of conductivity modulation, in addition to the usual characterization by diffusion capacitance, transition capacitance, and an ideal junction. It is shown that this model employed in a switching circuit exhibits the overshoot and oscillation characteristic of diodes at high forward currents, as well as the usual charge storage effects for the reverse transient. Using small-signal analysis it is shown that in some cases the model possesses an inductive impedance which is also characteristic of diodes at high forward currents.

CAMAC: a modular standard

Describes the basic IEEE specifications of CAMAC, acquaints practising system engineers with its basic principles and applications, and gives insight into how this standard can benefit the digital engineering community.

The SLAC Mark II Upgrade Drift Chamber Front End Electronics

The SLAC Mark II detector is being improved by the addition of a new main drift chamber and associated electronics to prepare it for operation as the first detector at SLC. Presented here are the initial signal processing electronics, the preamplifiers, amplifiers and discriminators for the 5832 sense wires, which are located on the detector itself. The performance of the detector is established almost entirely by the drift chamber and this electronics.

Design of a FASTBUS Programmable Sequencer Module and Memory Module

A programmable sequencer and a memory module have been designed and built to demonstrate high speed operation of the FASTBUS, and to study design implications of the FASTBUS specification. Both are implemented in ECL, and illustrate master and slave operation, arbitration circuit design, and logical and geographical addressing considerations.

FASTBUS Demonstration Systems

This paper will provide a demonstration of basic FASTBUS hardware and test software. The systems will include single crate segments, simple computer I/O, a fast sequencer and memory, some simple diagnostic and display devices and a UNIBUS to FASTBUS processor interface. The equipment will be set up to show the basic FASTBUS protocols and timing transactions, as well as some of the general initialization software features.

FASTBUS Introduction and Demonstration

A brief explanation of the FASTBUS protocol has been given along with a short description of the 3 FASTBUS modules and operating system which are being used in the initial prototyping and verification efforts.

The Confusing Digital Standards Picture--Are They Related?

Due to the realization of international competition and the recognition that perhaps the time for action has arrived, there recently has been a flurry of activity in many areas of digital interfacing standards. This paper will review the status and discuss the relation of the CAMAC system, the IEC bus, the channel interface, and the new bit serial standards in terms of the nuclear instrument, process control, and general computation communities.

Versatile, Modular Readout System for CAMAC Scalers

A display and readout system for CAMAC scalers will be described which has been in use at SLAC for over a year. Flexibility and versatility are the keynotes of the system, which includes a modular quad display unit employing highly readable Nixie tubes. Other units which may be connected to the expandable bus include an X-Y scope display and a preset count module. The system employs a simple, but versatile CAMAC crate controller. Capability for connection to computers is included, and the system has been interfaced to several different computers.

Simple CAMAC Test System Based on the S-100 Bus

A simple CAMAC test system based upon the use of the S-100 (Hobbyist) bus has been implemented at SLAC. The IMSAI 8080 computer is used, containing 16K bytes of RAM and 1K bytes of EPROM. All programming and operator interaction takes place via a thermal printer-keyboard, and all test programs are written in IMSAI BASIC. The system has been used to test components, CAMAC modules, and complex CAMAC systems.

Analysis and simulation of the SLD WIC PADS hybrid preamplifier circuitry

Computer simulation techniques are used to analyze critical performance parameters of the SLD PADS preamplifier hybrid, including its interactions with the detector system. Simulation results are presented and verified with measured performance. The use of the computer simulation of the detector/preamplifier combination is shown to be a reasonably accurate predictor of preamplifier performance, but more importantly, it allows one to demonstrate, analyze, and quantify selected aspects of the hybrids behavior in the system. In particular, the analysis confirms wide tolerances on system timing and demonstrates that self-calibration can compensate for the effects of large variation in detector capacitance. The selection of 6 mu s for fixed time sampling is shown to be entirely reasonable for this system. >