B. Bertolucci

FASTBUS Dual-Port Memory and Display Diagnostic Module

A dual-port FASTBUS memory module has been designed as a diagnostic tool for both Crate and Cable Segments.

Design of a FASTBUS Programmable Sequencer Module and Memory Module

A programmable sequencer and a memory module have been designed and built to demonstrate high speed operation of the FASTBUS, and to study design implications of the FASTBUS specification. Both are implemented in ECL, and illustrate master and slave operation, arbitration circuit design, and logical and geographical addressing considerations.

Transceiver for the FASTBUS Cable Segment

A 4 mA differential transceiver circuit which meets the Fastbus Standard is described in this paper. It is planned to hybridize this circuit for use in Fastbus Cable Segment devices.

FASTBUS Demonstration Systems

This paper will provide a demonstration of basic FASTBUS hardware and test software. The systems will include single crate segments, simple computer I/O, a fast sequencer and memory, some simple diagnostic and display devices and a UNIBUS to FASTBUS processor interface. The equipment will be set up to show the basic FASTBUS protocols and timing transactions, as well as some of the general initialization software features.

FASTBUS Introduction and Demonstration

A brief explanation of the FASTBUS protocol has been given along with a short description of the 3 FASTBUS modules and operating system which are being used in the initial prototyping and verification efforts.

New Developments in Segment Ancillary Logic for FASTBUS

Segment Ancillary Logic hardware for FASTBUS systems provides logical functions required in common by all devices attached to a segment. It controls the execution of arbitration cycles, and geographical address cycles, and generates the system handshake responses for broadcast operations. The mandatory requirements for Segment Ancillary Logic in the FASTBUS specifications are reviewed. A detailed implementation based on ECL logic is described, and the hardware to be used on an ECL cable segment for an experimental FASTBUS system at SLAC is shown.

Monolithic transceiver for FASTBUS Cable Segment-CSX

Specifications for a five-channel differential transceiver for the FASTBUS Cable Segment have been developed. The transceiver, CSX, is being planned as a full-custom integrated circuit implementation. Specification and development plans are discussed. The project is being carried out in collaboration with the NIM/FASTBUS Committee. >

CAMAC Magnetostrictive Readout System Using Schottky Memories

A magnetostrictive readout modular system using fast TTL memories is described in this paper. The main characteristics of this system are its expandability, its simple logic configuration, its high recording speed and its capacity of 15 sparks/wand with a word length of 16 bits per spark.

Peppo A Dual Digital Delay and Gate Generator

A new high performance two-channel gate generator in a triple NIM module using integrated circuits is described. Its main characteristics are the digital design and the generation of both delay and width of a signal, relative to a trigger pulse, in each channel.

A Proportional Wire Chamber Electronics System Utilizing CAMAC

This report describes a system of electronics to be used with a proportional wire chamber hodoscope. The system, which uses CAMAC packaging and data handling philosophy, consists of octo (8 channel) wire signal amplifiers, octo 4-bit per wire latch modules, gate fanout modules, crate controllers, and two types of data processor-interface units to the SDS 9300 computer. System operation is explained, and each component is described.