D. J. Rieger

Inductively coupled plasma etching of GaN

Inductively coupled plasma (ICP) etch rates for GaN are reported as a function of plasma pressure, plasma chemistry, rf power, and ICP power. Using a Cl2/H2/Ar plasma chemistry, GaN etch rates as high as 6875 A/min are reported. The GaN surface morphology remains smooth over a wide range of plasma conditions as quantified using atomic force microscopy. Several etch conditions yield highly anisotropic profiles with smooth sidewalls. These results have direct application to the fabrication of group‐III nitride etched laser facets.

HIGH-DENSITY PLASMA ETCHING OF COMPOUND SEMICONDUCTORS

Inductively coupled plasma (ICP) etching of GaAs, GaP, and InP is reported as a function of plasma chemistry, chamber pressure, rf power, and source power. Etches were characterized in terms of rate and anisotropy using scanning electron microscopy, and root-mean-square surface roughness using atomic force microscopy. ICP etch rates were compared to electron cyclotron resonance etch rates for Cl2/Ar, Cl2/N2, BCl3/Ar, and BCl3/N2 plasmas under similar plasma conditions. High GaAs and GaP etch rates (exceeding 1500 nm/min) were obtained in Cl2-based plasmas due to the high concentration of reactive Cl neutrals and ions generated as compared to BCl3-based plasmas. InP etch rates were much slower and independent of plasma chemistry due to the low volatility of the InClx etch products. The surface morphology for all three materials was smooth over a wide range of etch conditions.

Sputtered AlN encapsulant for high‐temperature annealing of GaN

Reactively sputtered AlN is shown by electrical characterization of Pt/Au Schottky diodes to be an effect encapsulant for GaN annealed at 1100 °C. Schottky diodes formed on GaN encapsulated with AlN during the anneal had low reverse leakage currents with breakdown voltages in excess of 40 V. In contrast, samples annealed without the AlN layer had 3–4 orders‐of‐magnitude higher reverse leakage currents. Atomic force microscopy images of as‐grown and annealed samples also demonstrate an increase in surface roughness and a change in morphology of the uncapped samples following annealing. Auger electron spectroscopy supports the hypothesis that the AlN encapsulant is reducing N loss from the GaN substrate. N loss in the uncapped samples is expected to create an n+‐region at the surface that accounts for the high reverse leakage current and improved Ohmic behavior for the uncapped samples. The use of AlN encapsulation will enable the realization of all ion implanted GaN metal semiconductor field effect transis...

ULTRAHIGH SI+ IMPLANT ACTIVATION EFFICIENCY IN GAN USING A HIGH-TEMPERATURE RAPID THERMAL PROCESS SYSTEM

Si+ implant activation efficiencies above 90%, even at doses of 5×1015 cm−2, have been achieved in GaN by rapid thermal processing at 1400–1500 °C for 10 s. The annealing system utilizes molybdenum intermetallic heating elements capable of operation up to 1900 °C, producing high heating and cooling rates (up to 100 °C s−1). Unencapsulated GaN shows severe surface pitting at 1300 °C and complete loss of the film by evaporation at 1400 °C. Dissociation of nitrogen from the surface is found to occur with an approximate activation energy of 3.8 eV for GaN (compared to 4.4 eV for AlN and 3.4 eV for InN). Encapsulation with either rf magnetron reactively sputtered or metal organic molecular beam epitaxy-grown AlN thin films provides protection against GaN surface degradation up to 1400 °C, where peak electron concentrations of ∼5×1020 cm−3 can be achieved in Si-implanted GaN. Secondary ion mass spectrometry profiling showed little measurable redistribution of Si, suggesting DSi⩽10−13 cm2 s−1 at 1400 °C. The imp...

Comparison of Mg and Zn gate implants for GaAs n-channel junction field effect transistors

Zinc and magnesium implants into GaAs were profiled with secondary ion mass spectroscopy and etching capacitance-voltage to measure the as-implanted and annealed profiles for the eventual formation of shallow p+/n junction gates for junction field effect transistors (JFETs). The larger mass of the zinc ions results in shorter projected range with significantly less tailing than magnesium implants. High dose, shallow zinc implants annealed under tungsten gate metal showed good activation with negligible diffusion. The improved profile of the zinc implant, as compared to a similar magnesium implant, allowed a tighter JFET design with increased performance. Zn gated n-channel enhancement mode GaAs JFETs with 0.9 µm gate lengths showed transconductances up to 200 mS/ mm with a ft of 18 GHZ and a fmax of 37 GHz. The performance of these self-aligned fully implanted JFETs compare favorably with comparably sized implanted MESFETs.

Plasma‐induced damage of GaAs during etching of refractory metal contacts

The effect of plasma‐induced damage on the majority carrier transport properties of p‐type GaAs has been studied by monitoring changes in sheet resistance (Rs) of thin conducting layers under various plasma conditions including etch conditions for refractory metal contacts. Rs determined from transmission line measurements are used to evaluate plasma‐induced damage for electron cyclotron resonance (ECR) and reactive ion etch (RIE) conditions by varying the thickness and doping of epitaxial layers. Damage depths calculated from Rs data show a strong dependence on doping levels. This can be explained by a plasma‐damage‐induced trap density profile which tails off into the sample. Consistent trends have been observed where Rs increases with increasing dc bias, increasing microwave power, and decreasing pressure, thus showing Rs increases as either the ion energy or ion flux increases. The lowest plasma‐induced damage observed in this study occurs with ECR at low microwave power and no rf biasing. Under rf‐bi...

An all implanted self-aligned enhancement mode n-JFET with Zn gates for GaAs digital applications

An all implanted self-aligned n-channel JFET fabrication process is described where Zn implantation is used to form the p/sup +/ gate region. A refractory metal (W) gate contact is used to allow subsequent high temperature activation of the self-aligned Si source and drain implant. 0.7 /spl mu/m JFETs have a maximum transconductance of 170 mS/mm with a saturation current of 100 mA/mm at a gate bias of 0.9 V. The p/sup +//n homojunction gate has a turn on voltage of 0.95 V at a current of 1 mA/mm. The drain-source breakdown voltage is 6.5 V. Microwave measurements made at a gate bias of 1 V show an f/sub t/ of 19 GHz with an f/sub max/ of 36 GHz. These devices show promise for incorporation in both DCFL and complementary logic circuits.<<ETX>>

Redistribution and activation of implanted S, Se, Te, Be, Mg, and C in GaN

A variety of different possible donor and acceptor impurities have been implanted into GaN and annealed up to 1450 °C. S+ and Te+ produce peak electron concentrations ⩽5×1018 cm−3, well below that achievable with Si+. Mg produces p-type conductivity, but Be+- and C+- implanted samples remained n type. No redistribution was observed for any of the implanted species for 1450 °C annealing. Much more effective damage removal was achieved for 1400 °C annealing of high-dose (5×1015 cm−2) Si+ implanted GaN, compared to the more commonly used 1100 °C annealing.

Ecr Etching of GaP, GaAs, InP, and InGaAs in Cl 2 /Ar, Cl 2 /N 2 , BCl 3 /Ar, and BCl 3 /N 2

Electron cyclotron resonance (ECR) etching of GaP, GaAs, InP, and InGaAs are reported as a function of percent chlorine-containing gas for Cl 2 /Ar, Cl 2 /N 2 , BCl 3 /Ar, and BCl 3 /N 2 plasma chemistries. GaAs and GaP etch rates were faster than InP and InGaAs, independent of plasma chemistry due to the low volatility of the InCl x , etch products. GaAs and GaP etch rates increased as %Cl 2 was increased for Cl 2 /Ar and Cl 2 /N 2 plasmas. The GaAs and GaP etch rates were much slower in BCl 3 -based plasmas due to lower concentrations of reactive Cl, however enhanced etch rates were observed in BCl 3 /N 2 at 75% BCl 3 . Smooth etched surfaces were obtained over a wide range of plasma chemistries.

Complementary GaAs junction-gated heterostructure field effect transistor technology

The first circuit results for a new GaAs complementary logic technology are presented. The technology allows for independently optimizable p- and nchannel transistors with junction gates. Excellent loaded gate delays of 179 ps at 1.2 V and 319 ps at 0.8 V have been demonstrated at low power supply voltages. A power-delay product of 8.9 fJ was obtained at 0.8 V.