D. Nguyen-Ngoc

Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace

Early production results are reviewed for IBMs integrated SiGe HBT technology. With a sample size of over 200 wafers, statistical control of key HBT parameters (F/sub T/, F/sub max/, R/sub bb/, R/sub bi/, /spl beta/) and other supporting devices, and benchmark circuit performance are shown. HBT device yield and reliability on 200 mm wafers are presented, demonstrating that the SiGe HBT is capable of meeting manufacturing requirement for the high performance wireless communications marketplace.

SiGe HBT technology: device and application issues

SiGe HBT Bipolar/BiCMOS technology has a unique opportunity in the wireless marketplace because it can provide the performance of III-V HBTs and the integration/cost benefits of silicon bipolar/BiCMOS. This paper will review the status of IBMs SiGe HBT technology particularly focusing on some key device and application issues for high frequency circuit applications. In this work we review graded-base SiGe HBTs optimized for analog circuits and address four key issues: 1) BV/sub ceo/ constraints, 2) Transmission line loss, 3) Noise performance, and 4) Process integration leverage and issues. All of the hardware results are for self-aligned, polysilicon emitter, graded-base SiGe HBTs fabricated in a 200 mm semiconductor production line using the UHV/CVD technique for film growth.

Neutron radiation tolerance of advanced UHV/CVD SiGe HBT BiCMOS technology

The effects of 1.0 MeV neutron irradiation on both SiGe heterojunction bipolar transistors (HBTs) and Si CMOS transistors from an advanced ultra high vacuum chemical vapour deposition (UHV/CVD) SiGe BiCMOS technology are examined for the first time over the temperature range of 300 K to 84 K. Results at 300 K indicate that this SiGe technology is robust with respect to neutron radiation. At fluences as high as 10/sup 15/ n/cm/sup 2/ (1.0 MeV equivalent) the devices exhibited a degradation of less than 30% in peak current gain. The SiGe HBTs maintain a current gain of 60 after 10/sup 15/ n/cm/sup 2/ at 84 K, compared to the Si BJT which degrades with cooling to a current gain of 20 at 84 K. The cutoff frequencies of both the Si and SiGe transistors are unaffected by neutron irradiation, and only a slight degradation in the maximum oscillation frequency of the transistors was observed.

A 200 mm SiGe-HBT BiCMOS technology for mixed signal applications

A BiCMOS technology including 0.25 /spl mu/m electrical channel length (L/sub EFF/) nFET and pFET CMOS devices and 60 GHz f/sub max/ SiGe-HBT transistors has been achieved on 200 mm wafers. Both CMOS circuits and SiGe-HBT analog circuits were fabricated on the same chip to demonstrate the high integration capabilities of the technology. The CMOS circuits include CMOS ring oscillators and a 64 k SRAM with a 34 /spl mu/m/sup 2/ cell size. The SiGe-HBT circuits include ECL ring oscillators and a Voltage Controlled Oscillator (VCO). This is the highest level of integration yet achieved for any SiGe-base bipolar technology.

A 200 mm SiGe-HBT technology for wireless and mixed-signal applications

If SiGe-HBT technology is to successfully compete with GaAs technology in the rapidly emerging wireless communications market, it must demonstrate comparable performance, higher integration levels, compatibility with high volume production, and hence reduced costs. This work describes the first manufacturable 0.5 /spl mu/m SiGe-HBT technology for wireless communications applications which meets these requirements. The technology is currently installed on a 200 mm production line, using a commercial UHV/CVD system for SiGe film growth. AC transistor results (f/sub max/>45 GHz, power added efficiency=66%) demonstrate that this 200 mm SiGe technology is suitable for /spl ges/2.0 GHz RF applications. Record performance was achieved in a 1.2 GS/sec, <1.0 W 12-bit digital-to-analog convertor (DAC). Important manufacturing issues for high performance SiGe-HBTs which are addressed in this work include: SiGe epitaxial film defect densities, long-term device reliability, and device scaling.<<ETX>>

Large-signal performance of high-BV/sub CEO/ graded epi-base SiGe HBTs at wireless frequencies

To address the needs of 3 V wireless components such as power amplifiers, we have added a new, high-breakdown (6 V) HBT to IBMs 200 mm SiGe technology and explore the large-signal performance for the first time. At 0.9 GHz and 1.8 GHz, we observe excellent power densities of up to 1.36 mW//spl mu/m/sup 2/, outstanding PAE reaching 70% and no performance degradation in integrating the HBT with CMOS.

Manufacturability and applications of SiGe HBT technology

Abstract This article reviews the status of IBMs SiGe HBT technology, with a focus on manufacturability issues and circuit applications. Device design and process integration issues which have driven the development of the technology are discussed. Device results are shown, emphasizing the demonstration of reproducibility and yield in the manufacturing environment. Reproducibility of parameters for the 47/65 GHz (f T / f MAX ) SiGe HBT is shown to be superior to that of BJTs in state-of-the-art implanted-base processes. Recent circuit results, covering the performance range from 1 to 23 GHz, are reviewed. The addition of a polyimide/gold backend process for low-loss inductors and transmission lines is key to MMIC applications operating at 12 GHz and above.

A manufacturable poly-emitter graded-SiGe HBT technology for wireless and mixed-signal applications

Abstract Graded SiGe-base heterojunction transistors (HBTs) offer the advantages of bandgap engineering while maintaining the cost and manufacturing benefits of the silicon industry. For a technology to be widely used in the mixed signal applications arena it must offer more than just the HBT: it must have a complete set of passive elements and interconnects suitable for the rf design environment. This paper describes the development and current status of IBMs advanced SiGe HBT technology installed on a 200 mm CMOS/DRAM line. It reviews basic principles of HBT operation, discusses the aspects of the ultra high vacuum chemical vapor deposition (UHV/CVD) growth technique, describes the overall SiGe HBT process, the performance of the HBTs and support devices, and the circuit results achieved to data.

Impact of extrinsic base process on NPN HBT performance and polysilicon resistor in integrated SiGe HBTs

We have explored the process window for polysilicon resistor in the self-aligned epi-base HBT process utilizing various structure and implant conditions. We have performed a systematic study on the effects of implant energy, dosage, and polysilicon structure on the polysilicon resistor, p-i-n diode, and NPN performance. We find that the properties of this resistor can be controlled via the implant conditions, while leaving key HBT figures of merit such as f/sub T/, f/sub max/ virtually unchanged. We also demonstrate conditions resulting in a precision, low TCR resistor.

E-Beam Hot Spot Inspection for Early Detection of Systematic Patterning Problems for a 22 nm SOI Technology

Early detection of systematic patterning problems can provide a major boost for a technology team. Often in the past, these type defects might only be detected after functional test and subsequent failure analysis. At this point, three to six months of process development time have been lost and three to six months of defective hardware have been wasted. In this paper, a methodology for in-line detection of systematic patterning problems using E-beam hot spot inspection (EBHI) is introduced. Pattern simulation tools and other sources are used to recommend X, Y locations with challenging geometries for evaluation. EBHI evaluates the patterning capability for these locations using modulated wafers. A multifunction team addresses the hot spots that fail within the process window. EBHI is then used to evaluate the solutions proposed by this team. Often, additional data is necessary to determine the full yield impact. This methodology provided tremendous value for IBMs 22 nm SOI technology. Several examples illustrating this point are presented. Line monitoring after the process windows have been established is also discussed.