Kathryn T. Schonenberg

Self-aligned SiGe NPN transistors with 285 GHz f/sub MAX/ and 207 GHz f/sub T/ in a manufacturable technology

This paper reports on SiGe NPN HBTs with unity gain cutoff frequency (f/sub T/) of 207 GHz and an f/sub MAX/ extrapolated from Masons unilateral gain of 285 GHz. f/sub MAX/ extrapolated from maximum available gain is 194 GHz. Transistors sized 0.12/spl times/2.5 /spl mu/m/sup 2/ have these characteristics at a linear current of 1.0 mA//spl mu/m (8.3 mA//spl mu/m/sup 2/). Smaller transistors (0.12/spl times/0.5 /spl mu/m/sup 2/) have an f/sub T/ of 180 GHz at 800 /spl mu/A current. The devices have a pinched base sheet resistance of 2.5 k/spl Omega//sq. and an open-base breakdown voltage BV/sub CEO/ of 1.7 V. The improved performance is a result of a new self-aligned device structure that minimizes parasitic resistance and capacitance without affecting f/sub T/ at small lateral dimensions.

SiGe HBTs with cut-off frequency of 350 GHz

This work reports on SiGe HBTs with f/sub T/ of 350 GHz. This is the highest reported f/sub T/ for any Si-based transistor as well as any bipolar transistor. Associated f/sub max/ is 170 GHz, and BV/sub CEO/ and BV/sub CBO/ are measured to be 1.4 V and 5.0 V, respectively. Also achieved was the simultaneous optimization of f/sub T/ and f/sub max/ resulting in 270 GHz and 260 GHz, with BV/sub CEO/ and BV/sub CBO/ of 1.6 V and 5.5 V, respectively. The dependence of device performance on bias condition and device dimension has been investigated. Considerations regarding the extraction of such high f/sub T/ and f/sub max/ values are also discussed.

A 0.18 /spl mu/m BiCMOS technology featuring 120/100 GHz (f/sub T//f/sub max/) HBT and ASIC-compatible CMOS using copper interconnect

A BiCMOS technology is presented that integrates a high performance NPN (f/sub T/=120 GHz and f/sub max/=100 GHz), ASIC compatible 0.11 /spl mu/m L/sub eff/ CMOS, and a full suite of passive elements. Significant HBT performance enhancement compared to previously published results has been achieved through further collector and base profile optimization guided by process and device simulations. Base transit time reduction was achieved by simultaneously increasing the Ge ramp and by limiting the base diffusion with the addition of carbon doping to SiGe epitaxial base. This paper describes IBMs next generation SiGe BiCMOS production technology targeted at the communications market.

SiGe HBT technology with f/sub max//f/sub T/=350/300 GHz and gate delay below 3.3 ps

This work reports on SiGe HBT technology with f/sub max/ and f/sub T/ of 350 GHz and 300 GHz, respectively, and a gate delay below 3.3 ps. This is the highest reported speed for any Si-based transistor in terms of combined performance of f/sub max/ and f/sub T/ both of which exhibit 300 GHz and above. Associated BV/sub CEO/ and BV/sub CBO/ are measured to be 1.7 V and 5.6 V, respectively. The dependence of device performance on bias condition and device dimension has been investigated. Considerations regarding the extraction of such high f/sub max/ and f/sub T/ values are also discussed.

A 210-GHz f/sub T/ SiGe HBT with a non-self-aligned structure

A record 210-GHz f/sub T/ SiGe heterojunction bipolar transistor at a collector current density of 6-9 mA//spl mu/m/sup 2/ is fabricated with a new nonself-aligned (NSA) structure based on 0.18 /spl mu/m technology. This NSA structure has a low-complexity emitter and extrinsic base process which reduces overall thermal cycle and minimizes transient enhanced diffusion. A low-power performance has been achieved which requires only 1 mA collector current to reach 200-GHz f/sub T/. The performance is a result of narrow base width and reduced parasitics in the device. Detailed comparison is made to a 120-GHz self-aligned production device.

Manufacturability demonstration of an integrated SiGe HBT technology for the analog and wireless marketplace

Early production results are reviewed for IBMs integrated SiGe HBT technology. With a sample size of over 200 wafers, statistical control of key HBT parameters (F/sub T/, F/sub max/, R/sub bb/, R/sub bi/, /spl beta/) and other supporting devices, and benchmark circuit performance are shown. HBT device yield and reliability on 200 mm wafers are presented, demonstrating that the SiGe HBT is capable of meeting manufacturing requirement for the high performance wireless communications marketplace.

A 0.18 /spl mu/m 90 GHz f/sub T/ SiGe HBT BiCMOS, ASIC-compatible, copper interconnect technology for RF and microwave applications

We present a self-aligned, 0.18 /spl mu/m emitter width SiGe HBT with f/sub T/ of 90 GHz, f/sub MAX/ of 90 GHz (both at V/sub CB/=0.5 V), NF/sub MIN/ of 0.4 dB, and BV/sub CEO/ of 2.7 V. We also demonstrate that this device is integrable with IBMs 0.18 /spl mu/m, 1.8/3.3 V copper metallization CMOS technology with little effect on the CMOS device properties and design rules.

SiGe HBT technology: device and application issues

SiGe HBT Bipolar/BiCMOS technology has a unique opportunity in the wireless marketplace because it can provide the performance of III-V HBTs and the integration/cost benefits of silicon bipolar/BiCMOS. This paper will review the status of IBMs SiGe HBT technology particularly focusing on some key device and application issues for high frequency circuit applications. In this work we review graded-base SiGe HBTs optimized for analog circuits and address four key issues: 1) BV/sub ceo/ constraints, 2) Transmission line loss, 3) Noise performance, and 4) Process integration leverage and issues. All of the hardware results are for self-aligned, polysilicon emitter, graded-base SiGe HBTs fabricated in a 200 mm semiconductor production line using the UHV/CVD technique for film growth.

3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay

We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high f/sub MAX/ (338 GHz) and a low f/sub T/ (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) f/sub T/ and f/sub MAX/, a simple figure of merit proportional to /spl radic/f/sub T//R/sub B/C/sub CB/ with R/sub B/ and C/sub CB/ extracted from S-parameter measurement is best correlated to the minimum gate delay.

A 200 mm SiGe-HBT BiCMOS technology for mixed signal applications

A BiCMOS technology including 0.25 /spl mu/m electrical channel length (L/sub EFF/) nFET and pFET CMOS devices and 60 GHz f/sub max/ SiGe-HBT transistors has been achieved on 200 mm wafers. Both CMOS circuits and SiGe-HBT analog circuits were fabricated on the same chip to demonstrate the high integration capabilities of the technology. The CMOS circuits include CMOS ring oscillators and a 64 k SRAM with a 34 /spl mu/m/sup 2/ cell size. The SiGe-HBT circuits include ECL ring oscillators and a Voltage Controlled Oscillator (VCO). This is the highest level of integration yet achieved for any SiGe-base bipolar technology.