Mack W. Riley

The design and implementation of a first-generation CELL processor

A CELL processor is a multi-core chip consisting of a 64b power architecture processor, multiple streaming processors, a flexible IO interface, and a memory interface controller. This SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of modularity and reuse to maximize the custom circuit content and achieve a high-frequency clock-rate.

Cell Broadband Engine Debugging for Unknown Events

The complexity of todays hundreds-of-million-transistor microprocessors all but guarantees imperfect first silicon, but leaves unanswered the question of what exactly will go wrong. This article describes features added to the cell broadband engine processor to enable debugging in the presence of such unknown events.

Testability features of the first-generation CELL processor

The first generation CELL processor presented a test challenge in that the chip incorporated multiple processing elements, several multi-gigahertz synchronous and asynchronous clock domains, and many custom design elements. The test objective for the CELL design was to have high test coverage and a small test time. In addition to the objectives mentioned above, the CELL test logic is designed to support a modular design point and support for partial good processing elements. This paper will give an overview of the manufacturing test elements that were designed into the CELL processor

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI

This paper describe the challenges of migrating the Cell Broadband Engine (Cell BE) design from a 65 nm SOI to a 45 nm twin-well CMOS technology on SOI with low-k dielectrics and copper metal layers using a mostly automated approach. A die micrograph of the 45 nm Cell BE is described here. The cycle-by-cycle machine behavior is preserved. The focuses are automated migration, power reduction, area reduction, and DFM improvements. The chip power is reduced by roughly 40% and the chip area is reduced by 34%.

Debug of the CELL Processor: Moving the Lab into Silicon

With 234 million transistors, making up 9 processing units and 3 asynchronous clock domains in a high speed design, the CELL processor clearly presents a challenge to debug work required during lab bring-up and test bring-up. Traditional multi-processing systems reap the benefit of standard system level debug practices, but as the system has moved into the silicon so must the access during bring-up. This paper explains some of the innovative debug features included in the CELL processor design that were critical for efficient bring-up in a limited access environment

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

This paper reviews the design challenges that current and future processors must face, with stringent power limits and high frequency targets, and the design methods required to overcome the above challenges and address the continuing Giga-scale system integration trend. This paper then describes the details behind the design methodology that was used to successfully implement a first-generation CELL processor - a multi-core SoC. Key features of this methodology are broad optimization with fast rule-based analysis engines using macro-level abstraction for constraints propagation up/down the design hierarchy, coupled with accurate transistor level simulation for detailed analysis. The methodology fostered the modular design concept that is inherent to the CELL architecture, enabling a high frequency design by maximizing custom circuit content through re-use, and balanced power, frequency, and die size targets through global convergence capabilities. The design has roughly 241 million transistors implemented in 90 nm SOI technology with 8 levels of copper interconnects and one local interconnect layer. The chip has been tested at various temperatures, voltages, and frequencies. Correct operation has been observed in the lab on first pass silicon at frequencies well over 4GHz.

The design methodology and implementation of a first-generation CELL processor: a multi-core SoC

This paper reviews the design challenges that current and future processors must face with stringent power limits and high frequency targets, and the design methods required to address the continuing system integration trends. This paper then describes the implementation of a first-generation CELL processor and the design methods used to overcome the above challenges. A CELL processor consists of a 64 bit power architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multicore SoC, implemented in 90nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.

The design and implementation of a first-generation CELL processor - a multi-core SoC

The implementation of a first-generation CELL processor that supports multiple operating systems including Linux consists of a 64 bit power processor element (PPE) and its L2 cache, multiple synergistic processor elements (SPE) (B. Flachs et al.) each with its own local memory (LS) (T. Asano et al.), a high bandwidth internal element interconnect bus (EIB), two configurable non-coherent I/O interfaces, a memory interface controller (MIC), and a pervasive unit that supports extensive test, monitoring, and debug functions. In conclusion, special circuit techniques, rules for modularity and reuse, customized clocking structures, and unique power and thermal management concepts were applied to optimize the design.

Implementation of the 65nm Cell Broadband Engine

The first generation cell broadband engine processor introduced the cell architecture that consists of nine processor cores fabricated in the 90 nm CMOS SOI technology. This paper describes the advances made by moving the cell broadband engine design from 90 nm CMOS SOI to 65 nm CMOS SOI.

Cell BE SOC Debug Features

The Cell BE processor incorporates a 64-bit Power Architecture processor coupled with eight Synergistic processors, a Flexible IO interface, and a memory interface controller that are all connected by a high speed element interconnect mechanism. The processor also supports multiple operating systems, including Linux. The challenge of bringing new architectures that operate at multi-Gigahertz functional and test speeds required additional attention to debug functions on the chip. This paper will explore some of the debug features that were added to the Cell BE design.