D.S. Su

Radiation hardness and lifetime studies of the VCSELs for the ATLAS SemiConductor Tracker

Studies have been performed on the radiation hardness of the type of VCSELs 2 that will be used in the ATLAS SemicConductor Tracker. The measurements were made using 30 MeVproton beams, 24 GeV /c proton beams and a gamma source. The lifetime of the devices after irradiation was studied. r 2002 Elsevier Science B.V. All rights reserved.

The design of 8-Gbps VCSEL drivers for ATLAS liquid Argon calorimeter upgrade

We present designs and preliminary test results of LOCld1 and LOCld4, VCSEL drivers in a commercial 0.25-mu m m Silicon-on-Sapphire (SoS) CMOS process for ATLAS liquid Argon calorimeter upgrade. Active shunt peaking, multiple-stage amplification and higher voltage supply are used to achieve the data rate of 8 Gbps. LOCld1 is a single channel VCSEL driver with a differential output, while LOCld4 has four channels with single-ended open-drain outputs. Both drivers have tunable modulation and peaking strength. Bias current for VCSEL is also embedded.

Cryogenic digital data links for the liquid argon time projection chamber

In this paper we present the cryogenic functionality of the components of data links for the Liquid Argon Time Projection Chamber (LArTPC), a potential far site detector technology of the Long-Baseline Neutrino Experiment (LBNE). We have confirmed that an LVDS driver can drive a 20-meter CAT5E twisted pair up to 1 gigabit per second at the liquid nitrogen temperature (77 K). We have verified that a commercial-off-the-shelf (COTS) serializer, a laser diode driver, laser diodes, optical fibers and connectors, and field-programming gate arrays (FPGA`s) continue to function at 77 K. A variety of COTS resistors and capacitors have been tested at 77 K. All tests we have conducted show that the cryogenic digital data links for the liquid argon time projection chamber are promising.

High-Speed Serial Optical Link Test Bench Using FPGA with Embedded Transceivers

We develop a custom Bit Error Rate test bench based on Altera’s Stratix II GX transceiver signal integrity development kit, demonstrate it on point-to-point serial optical link with data rate up to 5 Gbps, and compare it with commercial stand alone tester. The 8B/10B protocol is implemented and its effects studied. A variable optical attenuator is inserted in the fibre loop to induce transmission degradation and to measure receiver sensitivity. We report comparable receiver sensitivity results using the FPGA based tester and commercial tester. The results of the FPGA also shows that there are more one-tozero bit flips than zero-to-one bit flips at lower error rate. In 8B/10B coded transmission, there are more word errors than bit flips, and the total error rate is less than two times that of non-coded transmission. Total error rate measured complies with simulation results, according to the protocol setup.

The Design of a High Speed Low Power Phase Locked Loop

The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for the development of radiation tolerant, high speed and low power serializer ASIC. We have designed a phase locked loop using a commercial 0.25-μm Silicon-onSapphire (SoS) CMOS technology. Post-layout simulation indicates that tuning range is 3.79 – 5.01 GHz and power consumption is 104 mW. The PLL has been submitted for fabrication. The design and simulation results are presented.