D. Veksler

Metal oxide resistive memory switching mechanism based on conductive filament properties

By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament (CF) features controlling TiN/HfO2/TiN resistive memory (RRAM) operations. The leakage current through the dielectric is found to be supported by the oxygen vacancies, which tend to segregate at hafnia grain boundaries. We simulate the evolution of a current path during the forming operation employing the multiphonon trap-assisted tunneling (TAT) electron transport model. The forming process is analyzed within the concept of dielectric breakdown, which exhibits much shorter characteristic times than the electroforming process conventionally employed to describe the formation of the conductive filament. The resulting conductive filament is calculated to produce a non-uniform temperature profile along its length during the reset operation, promoting preferential oxidation of the filament tip. A thin dielectric barrier resulting from the CF tip oxidation is found to control filament resistance in the high resistive state. Field-driven dielectric breakdown of this barrier during the set operation restores the filament to its initial low resistive state. These findings point to the critical importance of controlling the filament cross section during forming to achieve low power RRAM cell switching.

Metal oxide RRAM switching mechanism based on conductive filament microscopic properties

By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament features controlling TiN/HfO2/TiN resistive memory operations. The forming process is found to define the filament geometry, which in turn determines the temperature profile and, consequently, the switching characteristics. The findings point to the critical importance of controlling filament dimensions during the forming process (polarity, max current/voltage, etc.).

Methodology for the statistical evaluation of the effect of random telegraph noise (RTN) on RRAM characteristics

We introduce a figure of merit (FoM) to quantify RRAM read current instability, a complex multi-level RTN-like signal, generally observed in read current. Log(FoM) follows a normal statistical distribution describing the probability of occurrence of a read current fluctuation of a given amplitude. We demonstrate that peak-to-peak RTN amplitude decreases with the reduction of the read current that enables scaling down RRAM operating currents. The developed statistical model for the read instability allows to estimate the maximum size and minimum operating current for reliable operations of high density RRAM array.

Positive Bias Instability and Recovery in InGaAs Channel nMOSFETs

Instability of InGaAs channel nMOSFETs with the Al2O3/ ZrO2 gate stack under positive bias stress demonstrates recoverable and unrecoverable components, which can be tentatively assigned to the pre-existing and generated defects, respectively. The recoverable component is determined to be primarily associated with the defects in the Al2O3 interfacial layer (IL), the slow trapping at which is responsible for the power law time dependency of the threshold voltage shift and transconductance change. The fast electron trapping in the ZrO2 film exhibits negligible recovery, in contrast to the Si-based devices with a similar high-k dielectric film. Generation of new electron trapping defects is found to occur in the IL, preferentially in the region close to the substrate, while trap generation in the high-k dielectric is negligible.

Leakage Current-Forming Voltage Relation and Oxygen Gettering in HfO x RRAM Devices

We observe a trend between initial leakage currents in polycrystalline HfOx resisitive random access memory (RRAM) cells (before forming) and the forming voltages. This trend points to the dominant role played by conduction paths located at grain boundaries, which is promoted by the oxygen deficiency in HfOx. One of these paths is then converted into the conductive filament responsible for nonvolatile resistance switching. In addition, we find that by engineering the RRAM stack, the forming voltage can be tuned-up to meet specific RRAM requirements, such as lower power and forming-less operations.

Controlling uniformity of RRAM characteristics through the forming process

The proposed constant voltage forming (CVF) is shown to increase the resistances of the low resistance and high resistance states while reducing their variability. By forcing the forming in all devices to occur at the same predefined voltage, the CVF method eliminates a major cause of the device-to-device variation associated with the randomness of the forming voltage values. Moreover, both experiments and simulations show that CVF at lower voltages suppresses the parasitic overshoot current, resulting in a more controlled and smaller filament cross-section and lower operation currents.

SILICON FINFETS AS DETECTORS OF TERAHERTZ AND SUB-TERAHERTZ RADIATION

We report on terahertz detection (from 0.2 THz to 2.4 THz) by Si FinFETs of different widths (with 2, 20, and 200 fins connected in parallel). FinFETs (with a small number of fins and with feature sizes as short as 20 nm to 40 nm) showed a very high responsivity (far above that previously measured for standard CMOS). We explain this improvement by negligible narrow channel effects.

Understanding noise measurements in MOSFETs: the role of traps structural relaxation

The presented theoretical analysis of random telegraph signal (RTS) and 1/f noise data provides consistent interpretation of the measurement results allowing trap characteristics to be extracted and the atomic structure of oxide traps to be identified. We emphasize the critical role of the lattice structural relaxation associated with charge trapping/detrapping, which represents one of the major factors controlling electron capture/emission times.

Analysis of Charge-Pumping Data for Identification of Dielectric Defects

We introduce a data analysis methodology for multifrequency charge-pumping (CP) measurements, which allows extracting both spatial and energy profiles of the CP-active traps in the gate dielectrics along with the defect energy characteristics. The analysis is based on the charge trapping/detrapping model accounting for carriers tunneling between the substrate and the oxide traps and multiphonon-assisted structural trap relaxation associated with charge carrier localization in the trap. Comparison of the spatial and energy trap distribution profiles obtained from CP data collected on a set of high-k dielectric gate stacks of different thicknesses facilitate the calibration of the model parameters. Extraction of the bulk trap characteristics, including trap ionization and relaxation energies, extends the utility of the CP technique from quantifying defect density toward identifying the nature of defects in the dielectric.

Errors Limiting Split-

The accuracy of the split-CV mobility extraction method is analyzed in buried-channel InGaAs MOSFETs with a Al2O3 gate dielectric and an InP barrier, through a “simulated experiment” procedure using 2-D numerical device simulations that are preliminarily calibrated against experimental I-V and CV curves. The different error sources limiting the method accuracy are pointed out. It is suggested that, as a result of these errors, the split- CV method can appreciably underestimate the actual channel mobility in these devices, with an error of >;20% and >;50% on peak mobility and high-VGS mobility, respectively. The method should therefore not be adopted for accurate mobility measurement in this operating regime but only as a fast response technique providing a conservative estimation of channel mobility. Moreover, the method provides mobility values that rapidly drop below the peak value for decreasing VGS. It is shown that this behavior can be an artifact of the extraction method, which may mask physical mechanisms causing a real mobility drop with decreasing channel carrier density, such as Coulomb scattering mechanisms. This poses limitations to the adoption of split-CV mobility as a reference for mobility model assessment in this operating regime. The proposed methodology can be applied to other III-V FETs, including both heterostructure-based and inversion-mode devices.