C. Hobbs

Chloride molecular doping technique on 2D materials: WS2 and MoS2.

Low-resistivity metal-semiconductor (M-S) contact is one of the urgent challenges in the research of 2D transition metal dichalcogenides (TMDs). Here, we report a chloride molecular doping technique which greatly reduces the contact resistance (Rc) in the few-layer WS2 and MoS2. After doping, the Rc of WS2 and MoS2 have been decreased to 0.7 kΩ·μm and 0.5 kΩ·μm, respectively. The significant reduction of the Rc is attributed to the achieved high electron-doping density, thus a significant reduction of Schottky barrier width. As a proof-of-concept, high-performance few-layer WS2 field-effect transistors (FETs) are demonstrated, exhibiting a high drain current of 380 μA/μm, an on/off ratio of 4 × 10(6), and a peak field-effect mobility of 60 cm(2)/(V·s). This doping technique provides a highly viable route to diminish the Rc in TMDs, paving the way for high-performance 2D nanoelectronic devices.

Evidence of aluminum silicate formation during chemical vapor deposition of amorphous Al2O3 thin films on Si(100)

Using narrow nuclear reaction resonance profiling, aluminum profiles are obtained in ∼3.5 nm Al2O3 films deposited by low temperature (<400 °C) chemical vapor deposition on Si(100). Narrow nuclear resonance and Auger depth profiles show similar Al profiles for thicker (∼18 nm) films. The Al profile obtained on the thin film is consistent with a thin aluminum silicate layer, consisting of Al–O–Si bond units, between the silicon and Al2O3 layer. Transmission electron microscopy shows evidence for a two-layer structure in Si/Al2O3/Al stacks, and x-ray photoelectron spectroscopy shows a peak in the Si 2p region near 102 eV, consistent with Al–O–Si units. The silicate layer is speculated to result from reactions between silicon and hydroxyl groups formed on the surface during oxidation of the adsorbed precursor.

Fermi-level pinning at the polysilicon/metal-oxide interface-Part II

We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. Oxygen vacancies at polysilicon/HfO/sub 2/ interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.

Fermi level pinning at the polySi/metal oxide interface

We report here for the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. This fundamental characteristic also affects the observed polySi depletion. Device data and simulation results will be presented.

Compatibility of polycrystalline silicon gate deposition with HfO2 and Al2O3/HfO2 gate dielectrics

Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO2 and Al2O3 capped HfO2 gate dielectrics are reported. It can be generally stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto HfO2 results in electrical properties much worse compared to similar HfO2 films using platinum metal gates. However, depositing CVD silicon gates directly onto Al2O3 capped HfO2 showed greater than a 104 times reduction in gate leakage compared to the poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness.

Group IVB metal oxides high permittivity gate insulators deposited from anhydrous metal nitrates

The electrical performance of column IVB metal oxide thin films deposited from their respective anhydrous metal nitrate precursors show significant differences. Titanium dioxide has a high permittivity, but shows a large positive fixed charge and low inversion layer mobility. The amorphous interfacial layer is compositionally graded and contains a high concentration of Si-Ti bonds. In contrast, ZrO/sub 2/ and HfO/sub 2/ form well defined oxynitride interfacial layers and a good interface with silicon with much less fixed charge. The electron inversion layer mobility for an HfO/sub 2//SiO/sub x/N/sub y//Si stack appears comparable to that of a conventional SiO/sub 2//Si interface.

Dual-metal gate CMOS with HfO 2 gate dielectric

We report for the first time on a novel dual-metal gate CMOS integration on HfO/sub 2/ gate dielectric using TiN (PMOS) and TaSiN (NMOS) gate electrodes. Compared to a single metal integration, the dual-metal integration does not degrade gate leakage, mobility and charge trapping behavior. Promising preliminary TDDB data were obtained from dual-metal gate MOSFETs, while still delivering much improved gate leakage (10/sup 4/ - 10/sup 5/ X better than SiO/sub 2/).

PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology

We report here for the first time an evaluation of a polysilicon capped physical vapor deposited (PVD) titanium nitride (TiN) metal gate integration on sub-quarter micron CMOSFETs using bulk Si and FDSOI substrates. In addition to eliminating poly depletion effects and lowering gate line resistance, the use of the TiN gate enables lower Vt when used with FDSOI substrates instead of bulk Si. Excellent on-off and short channel characteristics can be obtained with the TiN gate. Issues associated with Leff and reliability are also discussed.

80 nm poly-Si gate CMOS with HfO/sub 2/ gate dielectric

We report here for the first time the formation of an amorphous oxide layer between the polysilicon gate and hafnium oxide (HfO/sub 2/) gate dielectric due to a lateral oxidation mechanism at the gate edge. Using a polySi reoxidation-free CMOS process, well behaved 80 nm MOSFETs were fabricated with no evidence of lateral oxidation. A CETinv of 25 /spl Aring/ with a leakage current 1000/spl times/ lower than SiO/sub 2/ was obtained for a 30 /spl Aring/ HfO/sub 2//12 /spl Aring/ interfacial oxide stack. In this paper, we present results on the physical and electrical characterization.

Positive Bias Instability and Recovery in InGaAs Channel nMOSFETs

Instability of InGaAs channel nMOSFETs with the Al2O3/ ZrO2 gate stack under positive bias stress demonstrates recoverable and unrecoverable components, which can be tentatively assigned to the pre-existing and generated defects, respectively. The recoverable component is determined to be primarily associated with the defects in the Al2O3 interfacial layer (IL), the slow trapping at which is responsible for the power law time dependency of the threshold voltage shift and transconductance change. The fast electron trapping in the ZrO2 film exhibits negligible recovery, in contrast to the Si-based devices with a similar high-k dielectric film. Generation of new electron trapping defects is found to occur in the IL, preferentially in the region close to the substrate, while trap generation in the high-k dielectric is negligible.