Dabraj Sarkar

A novel low cost 25μm thin exfoliated monocrystalline Si solar cell technology

To achieve grid parity, photovoltaic (PV) technologies must reduce the production cost of PV modules to well below

Single heterojunction solar cells on exfoliated flexible ∼25 μm thick mono-crystalline silicon substrates

1/Wp. In crystalline Si (c-Si) solar cells the cost of raw Si wafers is over 40% of the module cost. There is an industry wide push to reduce the active Si content of the cell through a combination of thinner wafers and increased cell efficiency. However, cell manufacturers are struggling to reduce the wafer thickness below 150μm as there are no economically viable technologies for manufacturing very thin Si wafers and such thin silicon wafers impose stringent handling requirements as wafer breakage and yield loss impact final module cost. In this paper, we demonstrate for the first time, a novel exfoliation technology capable of producing large area (6-in diameter) 25μm thin flexible mono c-Si foils that will dramatically change the cost structure and form factor of high efficiency-Si solar cells without the yield losses and handling issues that are a major problem for traditional thin Si wafers. An un-optimized single side heterojunction cell has been formed with a 25μm exfoliated c-Si foil, which shows an efficiency of 12.5%. The cell characteristics of a 25μm thin c-Si cell with intrinsic a-Si passivation will be presented in the paper. Simulations show that with optimized texturing of the foil and passivation, higher efficiencies (20%) can be attained. Depending on the starting wafer or ingot thickness a final cell cost of between

Back-contact solar cells in thin crystalline silicon

0.46/Wp to

Mechanical strength and reliability of a novel thin monocrystalline silicon solar cell

0.50/Wp can be achieved compared to

Realization of dual-heterojunction solar cells on ultra-thin ∼25 μm, flexible silicon substrates

1.1/Wp for todays commercial thick crystalline Si cells.

An ultra-fast floating-body/gate cell for embedded DRAM

Mono-crystalline silicon single heterojunction solar cells on flexible, ultra-thin (∼25 μm) substrates have been developed based on a kerf-less exfoliation method. Optical and electrical measurements demonstrate maintained structural integrity of these flexible substrates. Among several single heterojunction ∼25 μm thick solar cells fabricated with un-optimized processes, the highest open circuit voltage of 603 mV, short circuit current of 34.4 mA/cm2, and conversion efficiency of 14.9% are achieved separately on three different cells. Preliminary reliability test results that include thermal shock and highly accelerated stress tests are also shown to demonstrate compatibility of this technology for use in photovoltaic modules.

A low cost kerfless thin crystalline Si solar cell technology

A novel kerf-free process for achieving crystalline silicon with thickness ≅25µm on metal (SOM) is overviewed, and fabrication of back-contact (BC) solar cells in the thin silicon wafers is described. An object-oriented 2-D device simulator is set up for reliable physics-based numerical simulation of thin-Si solar cells, and is used to define optimal design of the thin BCSOM cell and to predict its ultimate performance. An efficiency approaching 20% is projected, and supporting preliminary experimental results are presented.

Exfoliated thin, flexible monocrystalline germanium heterojunction solar cells

Thin crystalline silicon solar cells, on the order of a few to tens of μm thick, are of interest due to significant material cost reduction and potentially high conversion efficiency. These thin silicon films impose stringent mechanical strength and handling requirements during wafer transfer, cell processing and module integration. Quantitative mechanical and fracture analyses to address reliability issues become necessary. Based on a bi-material foil composed of thin monocrystalline silicon and a supporting substrate fabricated from a novel SOM® (Semiconductor on Metal) kerf-less exfoliation process, closed-form mechanical analyses are introduced and developed to evaluate their strength and fracture behaviors. These analyses include the thermal stress field in the device silicon layer and supporting substrate, the fracture behavior and effects of pyramid structures from surface texturing and the energy release rate at the silicon-substrate interface. It is shown that the introduction of the intrinsic compressive residual strain in the SOM® substrate expands the processing temperature spectrum. The developed analysis and methodology can be readily extended to other thin film solar cell structures with various configurations of device layers and supporting substrates.

Exfoliated, thin, flexible germanium heterojunction solar cell with record FF ¼58.1%

Silicon heterojunction (HJ) solar cells with different rear passivation and contact designs were fabricated on ∼25 μm semiconductor-on-metal (SOM) exfoliated substrates. It was found that the performance of these cells is limited by recombination at the rear-surface. Employing the dual-HJ architecture resulted in the improvement of open-circuit voltage (Voc) from 605 mV (single-HJ) to 645 mV with no front side intrinsic amorphous silicon (i-layer) passivation. Addition of un-optimized front side i-layer passivation resulted in further enhancement in Voc to 662 mV. Pathways to achieving further improvement in the performance of HJ solar cells on ultra-thin SOM substrates are discussed.

Remote plasma chemical vapor deposition for high-efficiency ultra-thin ∼25-microns crystalline Si solar cells

Floating-body DRAM cells (FBCs) on SOI are of interest because of integration problems associated with the large storage capacitor of nanoscale conventional 1T/ 1C DRAM. However, limitations on FBC speed, due to relatively slow write times governed by the usual impact-ionization or tunneling body-charging processes, preclude the application of most interest - embedded DRAM. We recently proposed a novel 2T (T1 and T2) FBC, i.e., a floating-body/gate cell (FBGC) , which enables design flexibility for optimizing performance. We present herein a new 2T design concept (FBGC4) that gives ultra-fast write times, in addition to good current-signal margin and long retention times, and thus enables the embedded-DRAM application. Further, low power and good reliability are implied because of low-voltage operation afforded by FBGC4.