Dharmesh Jawarani
Freescale Semiconductor
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Publication
Featured researches published by Dharmesh Jawarani.
photovoltaic specialists conference | 2011
Rajesh Rao; Leo Mathew; Sayan Saha; Scott Smith; Dabraj Sarkar; R. Garcia; R. Stout; A. Gurmu; E. U. Onyegam; D. Ahn; Dewei Xu; Dharmesh Jawarani; J. G. Fossum; Sanjay K. Banerjee
To achieve grid parity, photovoltaic (PV) technologies must reduce the production cost of PV modules to well below
Applied Physics Letters | 2013
Sayan Saha; Mohamed M. Hilali; E. U. Onyegam; Dabraj Sarkar; Dharmesh Jawarani; Rajesh Rao; Leo Mathew; Ryan S. Smith; Dewei Xu; Ujjwal Das; Bhushan Sopori; Sanjay K. Banerjee
1/Wp. In crystalline Si (c-Si) solar cells the cost of raw Si wafers is over 40% of the module cost. There is an industry wide push to reduce the active Si content of the cell through a combination of thinner wafers and increased cell efficiency. However, cell manufacturers are struggling to reduce the wafer thickness below 150μm as there are no economically viable technologies for manufacturing very thin Si wafers and such thin silicon wafers impose stringent handling requirements as wafer breakage and yield loss impact final module cost. In this paper, we demonstrate for the first time, a novel exfoliation technology capable of producing large area (6-in diameter) 25μm thin flexible mono c-Si foils that will dramatically change the cost structure and form factor of high efficiency-Si solar cells without the yield losses and handling issues that are a major problem for traditional thin Si wafers. An un-optimized single side heterojunction cell has been formed with a 25μm exfoliated c-Si foil, which shows an efficiency of 12.5%. The cell characteristics of a 25μm thin c-Si cell with intrinsic a-Si passivation will be presented in the paper. Simulations show that with optimized texturing of the foil and passivation, higher efficiencies (20%) can be attained. Depending on the starting wafer or ingot thickness a final cell cost of between
photovoltaic specialists conference | 2010
J. G. Fossum; Dabraj Sarkar; Leo Mathew; Rajesh Rao; Dharmesh Jawarani; M. E. Law
0.46/Wp to
international reliability physics symposium | 2012
Dewei Xu; Paul S. Ho; Rajesh Rao; Leo Mathew; Scott Smith; Sayan Saha; Dabraj Sarkar; Curt Vass; Dharmesh Jawarani
0.50/Wp can be achieved compared to
Applied Physics Letters | 2014
E. U. Onyegam; Dabraj Sarkar; Mohamed M. Hilali; Sayan Saha; Leo Mathew; Rajesh Rao; Ryan S. Smith; Dewei Xu; Dharmesh Jawarani; R. Garcia; M. Ainom; Sanjay K. Banerjee
1.1/Wp for todays commercial thick crystalline Si cells.
photovoltaic specialists conference | 2012
Rajesh Rao; Leo Mathew; Dabraj Sarkar; Scott Smith; Sayan Saha; R. Garcia; R. Stout; A. Gurmu; M. Ainom; E. U. Onyegam; Dewei Xu; Dharmesh Jawarani; J. G. Fossum; Sanjay K. Banerjee; Ujjwal Das; Ajay Upadhyaya; Ajeet Rohatgi; Q. Wang
Mono-crystalline silicon single heterojunction solar cells on flexible, ultra-thin (∼25 μm) substrates have been developed based on a kerf-less exfoliation method. Optical and electrical measurements demonstrate maintained structural integrity of these flexible substrates. Among several single heterojunction ∼25 μm thick solar cells fabricated with un-optimized processes, the highest open circuit voltage of 603 mV, short circuit current of 34.4 mA/cm2, and conversion efficiency of 14.9% are achieved separately on three different cells. Preliminary reliability test results that include thermal shock and highly accelerated stress tests are also shown to demonstrate compatibility of this technology for use in photovoltaic modules.
photovoltaic specialists conference | 2011
E. U. Onyegam; Jason Mantey; Rajesh Rao; Leo Mathew; Mohamed M. Hilali; Sayan Saha; Dharmesh Jawarani; Scott Smith; D. A. Ferrer; S. V. Sreenivasan; Sanjay K. Banerjee
A novel kerf-free process for achieving crystalline silicon with thickness ≅25µm on metal (SOM) is overviewed, and fabrication of back-contact (BC) solar cells in the thin silicon wafers is described. An object-oriented 2-D device simulator is set up for reliable physics-based numerical simulation of thin-Si solar cells, and is used to define optimal design of the thin BCSOM cell and to predict its ultimate performance. An efficiency approaching 20% is projected, and supporting preliminary experimental results are presented.
international soi conference | 2007
Stefan Zollner; Paul A. Grudowski; Aaron Thean; Dharmesh Jawarani; Gauri V. Karve; Ted R. White; Scott Bolton; Heather Desjardins; Murshed M. Chowdhury; Kyuhwan Chang; Mo Jahanbani; R. Noble; L. Lovejoy; Marc A. Rossow; Dean J. Denning; Darren V. Goedeke; Stanley L. Filipiak; R. Garcia; Mark Raymond; Veer Dhandapani; Da Zhang; Laegu Kang; Phil Crabtree; X. Zhu; Mike Kottke; R. Gregory; Peter Fejes; X.-D. Wang; D. Theodore; William J. Taylor
Thin crystalline silicon solar cells, on the order of a few to tens of μm thick, are of interest due to significant material cost reduction and potentially high conversion efficiency. These thin silicon films impose stringent mechanical strength and handling requirements during wafer transfer, cell processing and module integration. Quantitative mechanical and fracture analyses to address reliability issues become necessary. Based on a bi-material foil composed of thin monocrystalline silicon and a supporting substrate fabricated from a novel SOM® (Semiconductor on Metal) kerf-less exfoliation process, closed-form mechanical analyses are introduced and developed to evaluate their strength and fracture behaviors. These analyses include the thermal stress field in the device silicon layer and supporting substrate, the fracture behavior and effects of pyramid structures from surface texturing and the energy release rate at the silicon-substrate interface. It is shown that the introduction of the intrinsic compressive residual strain in the SOM® substrate expands the processing temperature spectrum. The developed analysis and methodology can be readily extended to other thin film solar cell structures with various configurations of device layers and supporting substrates.
CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2007 International Conference on Frontiers of Characterization and Metrology | 2007
Stefan Zollner; Richard B. Gregory; Mike Kottke; Victor H. Vartanian; X.-D. Wang; D. Theodore; Peter Fejes; James Conner; Mark Raymond; Xiaoyan Zhu; Dean J. Denning; Scott Bolton; Kyuhwan Chang; R. Noble; Mohamad M. Jahanbani; Marc A. Rossow; Darren V. Goedeke; Stan Filipiak; R. Garcia; Dharmesh Jawarani; Bill Taylor; Bich-Yen Nguyen; P. E. Crabtree; Aaron Thean
Silicon heterojunction (HJ) solar cells with different rear passivation and contact designs were fabricated on ∼25 μm semiconductor-on-metal (SOM) exfoliated substrates. It was found that the performance of these cells is limited by recombination at the rear-surface. Employing the dual-HJ architecture resulted in the improvement of open-circuit voltage (Voc) from 605 mV (single-HJ) to 645 mV with no front side intrinsic amorphous silicon (i-layer) passivation. Addition of un-optimized front side i-layer passivation resulted in further enhancement in Voc to 662 mV. Pathways to achieving further improvement in the performance of HJ solar cells on ultra-thin SOM substrates are discussed.
photovoltaic specialists conference | 2012
E. U. Onyegam; Dabraj Sarkar; Mohamed M. Hilali; Sayan Saha; Rajesh Rao; Leo Mathew; Dharmesh Jawarani; William James; Jason Mantey; M. Ainom; R. Garcia; Sanjay K. Banerjee
The crystalline Si photovoltaic industry has been scaling down the Si wafer thickness in order to reduce costs and potentially attain higher efficiencies by minimizing bulk recombination. However, cell manufacturers are struggling to reduce the wafer thickness below 150μm as there are no economically viable technologies for manufacturing very thin Si wafers and such thin silicon wafers impose stringent handling requirements as wafer breakage and yield loss impact final module cost. We have previously reported a novel kerfless exfoliation technology capable of producing ultra thin 25μm thin flexible mono c-Si foils from thick Si wafers. In this work, we report on scaling the technology to 8-inch diameter wafers. A 25μm thin exfoliated monocrystalline Si solar cell with a front heterojunction emitter and a diffused back surface field structure has been fabricated with a power conversion efficiency of 14.9%. Simulations show that with optimized texturing of the foil and better surface passivation, higher efficiencies (20%) can be attained. We have also fabricated dual heterojunction devices on 25μm thin exfoliated Si, which show high Voc of 680mV. Due to the kerfless exfoliation process and wafer reuse, a final cell cost of