Dae Geun Yang

Tall FIN formation for FINFET devices of 20nm and beyond using multi-cycles of passivation and etch processes

In the past a few years, there has been a trend that non-planar field effect transistors (FETs) replace planar counterparts in semiconductor industry. One of critical and challenging processes to fabricate this non-planar device in bulk Si wafers is forming the array of tall Si fins with tight pitch that is used for gate channel as well as source and drain. Fin formation process typically involves deep Si etch using hard mask formed by double patterning technique (DPT). Traditional Si etch tends to results in intra-cell depth loading due to pitch walking and necking profile at the top portion of fins due to deep Si etch at small space. In addition, tall fins tend to stick to each other after post etch wet clean due to surface tension and hydrophilic fin sidewall. In this publication, 200nm tall fins with straight profile at the significant top portion of fins are demonstrated by using multi cycles of passivation and etch process. Physical and chemical parameters of each cycle were tuned respectively to generate straight top profile for gate channel control and smooth bottom profile to make it friendly for the following oxide gap fill process. Intra-cell and iso-dense depth loading is less than 3% of total depth. In addition, fin sticking is no longer observed after this multi cycle process. The exact mechanism is still under investigation but it is postulated that the fin sidewall surface condition has changed to be less hydrophilic due to multi cycle passivation.