Daehwan Ahn

Tunneling MOSFET technologies using III-V/Ge materials

The critical issues, technical challenges and viable technologies of tunneling MOSFETs (TFET) utilizing III-V/Ge materials are examined in this study. N-channel TFETs using InGaAs bulk and quantum well (QW) homo-junctions, GaAsSb/InGaAs type-II hetero-junctions and Ge/strained SOI type-II hetero-junction are fabricated with emphasis on the superior source p⁺/n junction formation and the electrical properties are experimentally evaluated. It is found that InGaAs/In<inf>0.7</inf>Ga<inf>0.3</inf>As(3nm)/InGaAs QW n-TFETs with W/HfO<inf>2</inf>/Al<inf>2</inf>O<inf>3</inf> gate stacks (CET of 1.4 nm) exhibit the minimum sub-threshold swing (S.S.<inf>min</inf>) of 55 mV/dec. at room temperature, thanks to the steep-profile and defect-less Zn diffused p⁺/n source. Also, C-doped p+ GaSb/InAs and C-doped p⁺ GaAsSb/InGaAs n-TFETs on Si substrates are realized by employing direct wafer bonding. In addition, in-situ B-doped Ge/strained-Si hetero-junction TFETs are presented. P⁺ Ge/SOI n-TFETs with 1.1% bi-axial tensile strain exhibit steep S.S.<inf>min</inf> below 30 mV/dec. and large I<inf>on</inf>/I<inf>off</inf> over 10⁷.

Performance improvement of In x Ga 1−x As Tunnel FETs with Quantum Well and EOT scaling

In_0.53Ga_0.47As/In_xGa_1-xAs/In_0.53Ga_0.47As Quantum Well (QW) structure Tunnel FETs (TFETs) has been proposed and demonstrated. The systematic QW In content and thickness dependence on the TFET performance was quantitatively examined. The QW TFETs can significantly enhance the tunneling probability and resulting on-current (I_on) by lower bandgap (E_g) of the higher In content InGaAs than bulk In_xGa_1-xAs TFETs, while the increase in the off current (I_off) can be suppressed by source junction formation in low In content In_0.53Ga_0.47As regions. The minimum sub-threshold swing (S.S._min) of 62 mV/dec was obtained at V_D=150mV in the In_0.53Ga_0.47As/In_xGa_1-xAs (3nm)/In_0.53Ga_0.47As QW structure. Also, the highest I_on of 56μA/μm at V_D=1V among the fabricated InGaAs QW TFETs was obtained by In_0.53Ga_0.47As/InAs(5 nm)/In_0.53Ga_0.47As QW structure. We have also realized EOT-scaled bulk In_0.53Ga_0.47As TFETs with 1.7nm-CET HfO₂ (2.7nm)/Al₂O₃ (0.3nm) gate stacks, exhibiting S.S_min of 57 mV/dec at V_D=100 mV.

Relationship between interface state generation and substrate hole current in InGaAs metal-oxide-semiconductor (MOS) interfaces

The relationship between substrate hole currents and interface state generation in Al2O3/InGaAs n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) is experimentally studied for the MOSFETs with three different Al2O3 thicknesses of 3.2, 5.2, and 8.2 nm. The constant positive gate bias stress is applied. Then, the substrate hole current, monitored in the carrier separation setup, is clearly observed for the InGaAs n-channel MOSFETs. It is found that the density of the generated interface states (ΔDit) is uniquely represented as a function of the total hole fluence (Nhole), given by integrating the substrate hole current over time, not the total electron fluence. This experimental result strongly supports that interface state generation is triggered by holes induced by electrical stress, regardless of the thickness of Al2O3. It is also found that ΔDit in 3.2- and 5.2-nm-thick Al2O3 MOSFETs, expressed by the universal single line against Nhole, is lower than that in 8.2-nm-thick Al2O3 MOSFETs, which can be explained by the difference of the origin of the hole generation in the Al2O3/InGaAs metal-oxide-semiconductor interface. Judging from the similarity of these features with ΔDit in SiO2/Si n-MOSFETs reported previously, the Al2O3/InGaAs interfaces have the same physical origin of interface state generation as SiO2/Si interfaces.The relationship between substrate hole currents and interface state generation in Al2O3/InGaAs n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) is experimentally studied for the MOSFETs with three different Al2O3 thicknesses of 3.2, 5.2, and 8.2 nm. The constant positive gate bias stress is applied. Then, the substrate hole current, monitored in the carrier separation setup, is clearly observed for the InGaAs n-channel MOSFETs. It is found that the density of the generated interface states (ΔDit) is uniquely represented as a function of the total hole fluence (Nhole), given by integrating the substrate hole current over time, not the total electron fluence. This experimental result strongly supports that interface state generation is triggered by holes induced by electrical stress, regardless of the thickness of Al2O3. It is also found that ΔDit in 3.2- and 5.2-nm-thick Al2O3 MOSFETs, expressed by the universal single line against Nhole, is lower than that in 8.2-nm-thick Al2O3 MOSF...

III–V-based low power CMOS devices on Si platform

CMOS utilizing high mobility III–V channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunnel FETs (TFETs) using III–V channel materials are regarded as one of the most promising steep slope devices for the ultra-low power applications. In this presentation, we address the critical issues for realizing III–V MOSFETs and TFETs on the Si CMOS platform. Viable technologies of MOS channel, gate stack, source/drain and tunnel junction formation are introduced for satisfying the device requirements. The electrical properties of ultrathin body InAs MOSFETs, InGaAs/Ge CMOS, InAs/GaSb CMOS, InGaAs TFETs and InGaAs/GaAsSb TFETs are presented.

Design and properties of planar-type tunnel FETs using In0.53Ga0.47As/InxGa1-xAs/In0.53Ga0.47As quantum well

Tunnel Field Effect Transistors (tunnel FETs) have been proposed using In0.53Ga0.47As/InxGa1-xAs/In0.53Ga0.47As Quantum Well (InxGa1-xAs QW) channels which improve their performance. It is expected in this structure that the high-In-content InxGa1-xAs QW layer with the lower bandgap can increase the tunneling current and resulting on-current (Ion), while the low-In-content In0.53Ga0.47As layer, where the source junction edge is mainly formed, can suppress the increase in the junction leakage current because of the higher bandgap. Considering the strain effect and the quantum confinement effect of the InxGa1-xAs QW layers, the In content and the QW thickness are designed carefully in terms of the reduction in the effective bandgap. The proposed tunnel FETs using the QW layers grown by Metal-organic Vapor Phase Epitaxy are fabricated, and the electrical and physical properties are systematically evaluated. It is found that the InxGa1-xAs QW can significantly enhance the performance of tunnel FETs. As expected in the calculation of the effective bandgap, the higher In content and thicker QW thickness lead to higher Ion, while the thinner QW thickness makes the sub-threshold swing (S.S.) steeper through the reduction in off-current (Ioff) and enhancement of carrier confinement. The minimum sub-threshold swing (S.S.min) of 62 mV/dec is obtained at VD = 150 mV for a tunnel FET with an In0.53Ga0.47As (2.6 nm)/In0.67Ga0.33 As (3.2 nm)/In0.53Ga0.47As (96.3 nm) QW structure. Also, the highest Ion of 11 μA/μm at VD = 150 mV and VG = 1 V, which is 8.5 times higher than 1.3 μA/μm of a control In0.53Ga0.47As tunnel FET, is obtained for a tunnel FET with an In0.53Ga0.47As (2.2 nm)/InAs (6.3 nm)/In0.53Ga0.47As (94.4 nm) QW structure. It is found that the InAs QW tunnel FETs with the InAs QW thicker than 5 nm significantly degrade by high junction leakage current attributed to the lattice relaxation.Tunnel Field Effect Transistors (tunnel FETs) have been proposed using In0.53Ga0.47As/InxGa1-xAs/In0.53Ga0.47As Quantum Well (InxGa1-xAs QW) channels which improve their performance. It is expected in this structure that the high-In-content InxGa1-xAs QW layer with the lower bandgap can increase the tunneling current and resulting on-current (Ion), while the low-In-content In0.53Ga0.47As layer, where the source junction edge is mainly formed, can suppress the increase in the junction leakage current because of the higher bandgap. Considering the strain effect and the quantum confinement effect of the InxGa1-xAs QW layers, the In content and the QW thickness are designed carefully in terms of the reduction in the effective bandgap. The proposed tunnel FETs using the QW layers grown by Metal-organic Vapor Phase Epitaxy are fabricated, and the electrical and physical properties are systematically evaluated. It is found that the InxGa1-xAs QW can significantly enhance the performance of tunnel FETs. As expect...

Effects of HfO2/Al2O3 gate stacks on electrical performance of planar In x Ga1− x As tunneling field-effect transistors

We study the impact of gate stacks on the electrical characteristics of Zn-diffused source In x Ga1− x As tunneling field-effect transistors (TFETs) with Al2O3 or HfO2/Al2O3 gate insulators. Ta and W gate electrodes are compared in terms of the interface trap density (D it) of InGaAs MOS interfaces. It is found that D it is lower at the W/HfO2/Al2O3 InGaAs MOS interface than at the Ta/HfO2/Al2O3 interface. The In0.53Ga0.47As TFET with a W/HfO2 (2.7 nm)/Al2O3 (0.3 nm) gate stack of 1.4-nm-thick capacitance equivalent thickness (CET) has a steep minimum subthreshold swing (SS) of 57 mV/dec, which is attributed to the thin CET and low D it. Also, the In0.53Ga0.47As (2.6 nm)/In0.67Ga0.33As (3.2 nm)/In0.53Ga0.47As (96.5 nm) quantum-well (QW) TFET supplemented with this 1.4-nm-thick CET gate stack exhibits a steeper minimum SS of 54 mV/dec and a higher on-current (I on) than those of the In0.53Ga0.47As TFET.