Mitsuru Takenaka

Enhancement technologies and physical understanding of electron mobility in III–V n-MOSFETs with strain and MOS interface buffer engineering

In this paper, we have investigated the electron transport properties under two types of mobility enhancement engineering, which are channel strain and MOS interface buffer engineering. We have demonstrated epitaxial-based biaxially strained In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs. Tensile strained In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs shows high peak mobility of 2150 cm²/Vs. Furthermore, we have demonstrated high performance InAs-OI(-on insulator) MOSFETs on Si substrate with MOS interface buffer layer by direct wafer bonding, showing high peak mobility of 3180 cm²/Vs. The scattering mechanisms for the electron mobility in thin body In<inf>x</inf>Ga<inf>1−x</inf>As(InAs)-OI MOSFETs have been systematically analyzed and identified, for the first time.

MOS interface and channel engineering for high-mobility Ge/III-V CMOS

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. However, the device/process/integration technologies of Ge/III-V n- and pMOSFETs for satisfying requirements of future node MOSFETs have not been established yet. In this paper, we address gate stack and channel engineering for improving the channel mobility and the MOS interface properties with emphasis on thin EOT and ultrathin body, which are mandatory in the future nodes. As for Ge MOSFETs, GeOx/Ge interfaces formed by plasma post oxidation are shown to realize thin EOT, low Dit and high mobility. HfO2/Al2O3/GeOx/Ge gate stacks exhibit record high electron and hole mobility under EOT of 0.76 nm. As for III-V MOSFETs, ultrathin InAs channels with MOS interface buffer layers are shown to provide high electron mobility under InAs thickness of 3 nm. The results of low Dit HfO2/Al2O3/InGaAs stacks with CET of 1.08 nm are also presented. A strategy to enhance electron mobility in InGaAs MOSFETs on a basis of physical understanding of the MOS interface properties including high Dit inside the conduction band is also addressed.

High Performance Extremely Thin Body InGaAs-on-Insulator Metal?Oxide?Semiconductor Field-Effect Transistors on Si Substrates with Ni?InGaAs Metal Source/Drain

The extremely thin body (ETB) InGaAs-on-insulator (-OI) metal–oxide–semiconductor field-effect transistors (MOSFETs) on Si substrates were demonstrated by using Ni–InGaAs alloy metal source/drain (S/D). It has been found that a light doping concentration of ~1016 cm-3 and indium-rich InGaAs channels (In0.7Ga0.3As) provide a high mobility of 1700 cm2 V-1 s-1 even in the channel thickness of 10 nm. This is the first demonstration of ETB III–V-OI MOSFETs combined with the metal S/D technology. We have also achieved excellent ID–VG characteristics with an Ion/Ioff ratio of over 105 and low SS of 120 mV/dec in 5-nm-thick In0.7Ga0.3As-OI MOSFETs.

Electron Mobility Enhancement of Extremely Thin Body In0.7Ga0.3As-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors on Si Substrates by Metal–Oxide–Semiconductor Interface Buffer Layers

The electron mobility enhancement of extremely thin body In0.7Ga0.3As-on-insulator (-OI) metal–oxide–semiconductor field-effect transistors (MOSFETs) on Si substrates by using In0.3Ga0.7As MOS interface buffer layers was demonstrated. The MOSFETs with the InGaAs thickness of 2/5/3 nm have exhibited the electron mobility of 2810 cm2 V-1 s-1 with an enhancement factor of 4.2 against that of Si MOSFET. We have examined the body thickness (Tbody) dependence of the electron mobility. It was found that a channel thickness fluctuation scattering mechanism strongly affects the mobility in Tbody of around 10 nm and thinner. The formation of a uniform and flat InGaAs-OI wafer is required for further improvements.

Impact of Fermi level pinning inside conduction band on electron mobility in InGaAs metal-oxide-semiconductor field-effect transistors

Combining the split capacitance-voltage method with Hall measurements revealed the existence of interface traps within the conduction band (CB) of InGaAs in metal-oxide-semiconductor (MOS) structures with Al2O3 (or HfO2)/InGaAs interfaces. The impact of these interface traps on inversion-layer mobilities in InGaAs MOS field-effect transistors with various interface structures was investigated. We found that the interface traps (>1013u2009cm−2 eV−1) induce Fermi level pining at an energy level 0.21–0.35u2009eV above the CB minimum, which degrades the mobilities in the high inversion carrier concentration region. Furthermore, the energy levels are tunable by changing the interface structures.

Biaxially strained extremely-thin body In0.53Ga0.47As-on-insulator metal-oxide-semiconductor field-effect transistors on Si substrate and physical understanding on their electron mobility

We report the electrical characteristics of strained In0.53Ga0.47As-on-insulator (-OI) metal-oxide-semiconductor field-effect-transistors (MOSFETs) on Si substrates fabricated by a direct wafer bonding (DWB) technique. 1.7% highly strained In0.53Ga0.47As-OI structures are fabricated on Si substrate by DWB. Strained In0.53Ga0.47As-OI MOSFETs with Ni-InGaAs metal source/drain (S/D) have been operated with high on-current (Ion)/off-current (Ioff) ratio of ∼105 and good current saturation in output characteristics. MOSFETs with 1.7% tensile strain exhibits 1.65u2009×u2009effective mobility (μeff) enhancement against In0.53Ga0.47As MOSFET without strain. We found that this μeff enhancement is attributed to the increase in mobile free electron concentration under tensile strain, which leads to the lowering in the conduction band minimum (CBM) and the increase in the energy difference between CBM and the Fermi level pinning position due to a large amount of interface states by Hall measurements.

High mobility CMOS technologies using III-V/Ge channels on Si platform

MOSFETs using channel materials with high mobility and low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to Ge and III-V channels. In this paper, possible solutions for realizing III-V/Ge MOSFETs on the Si platform are presented. The high quality III-V channel formation on Si substrates can be realized through direct wafer bonding. The gate stack formation is constructed on a basis of atomic layer deposition (ALD) Al 2 O 3 gate insulators for both InGaAs and Ge MOSFETs. As the source/drain (S/D) formation, Ni-based metal S/D is implemented for both InGaAs and Ge MOSFETs. By combining these technologies, we demonstrate successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.

Self-aligned metal S/D GaSb p-MOSFETs using Ni-GaSb alloys

GaSb has stirred a significant interest over the recent years, due to its high bulk electron/hole mobility and optoelectronic properties [1]. Particularly, the high hole mobility makes GaSb one of the III-V materials promising for p-MOSFETs and fully-integrated CMOS applications. However, the device technologies for GaSb MOSFETs have not been fully developed yet. In this work, we address a novel formation technology of source and drain (S/D) for GaSb p-MOSFETs. One of the problems of the S/D formation in GaSb (and generally III-V) is the low dopant solubility and the necessity of high temperature annealing for dopant activation. However, thermal stability of the GaSb/oxide interfaces is low and, therefore, a S/D formation process with low thermal budget is strongly required [2]. Also, for deeply-scaled MOSFET fabrication, self-aligned S/D formation is mandatory. For these reasons, we introduce a salicide-like self-aligned metal S/D process by using Ni into GaSb. In this study, we present the results of the characterization of Ni-GaSb alloys formed by direct reaction between Ni and GaSb, which are suitable for S/D in GaSb p-MOSFETs. Finally, we demonstrate, for the first time, a GaSb p-MOSFET with self-aligned Ni-GaSb alloy S/D, which allows us to fabricate MOSFETs at temperature as low as 250°C.

MOS interface engineering for high-mobility Ge CMOS

In this paper, we have discussed the fundamental properties of the germanium oxides formed by thermal oxidation and plasma post-oxidation as interfacial layers for Ge MOSFETs. The germanium oxides form high-quality Ge MOS interface with interface trap density of around 1011 cm-2eV-1. High-mobility Ge n-MOSFETs and p-MOSFETs have successfully been demonstrated even with EOT of less than 0.8 nm, exhibiting that the germanium oxides are the most promising interfacial layers for future Ge CMOS.

Physical understanding of electron mobility in asymmetrically strained InGaAs-on-insulator metal-oxide-semiconductor field-effect transistors fabricated by lateral strain relaxation

In this paper, we fabricated asymmetrically tensile-strained In0.53Ga0.47As-on-insulator (-OI) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a lateral strain relaxation technique. A stripe-like line structure, fabricated in biaxially strained In0.53Ga0.47As-OI can lead to the lateral strain relaxation and asymmetric strain configuration in In0.53Ga0.47As-OI with the channel width of 100u2009nm. We have found that the effective mobility (μeff) enhancement in In0.53Ga0.47As-OI MOSFETs with uniaxial-like asymmetric strain becomes smaller than that in In0.53Ga0.47As-OI MOSFETs with biaxial strain. We have clarified from a systematic analysis between the strain values and the μeff characteristics that this mobility behavior can be understood by the change of the energy level of the conduction band minimum due to the lateral strain relaxation.