Shinichi Takagi

(Invited) MOS Interface Control Technologies for III-V/Ge Channel MOSFETs

MOSFETs using channel materials with low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to III-V and Ge channels. However, one of the most critical issues for realizing Ge/III-V MOSFETs is gate insulator formation with superior MOS interface quality on Ge/III-V. In this paper, we focus on the possible solutions for gate stack technologies on Ge/III-V. As for Ge, GeO2/Ge interfaces have been regarded as promising. However, these interfaces have still employed thick GeO2 layers. Recently, we have succeeded in thin EOT gate stacks with Ge oxide interfacial layers by using ECR plasma post oxidation. The high quality Al2O3/GeOx/Ge gate stacks were fabricated by exposing the ALD Al2O3/Ge structures to ECR oxygen plasma and oxidizing the Ge surface through the very thin ALD Al2O3 layer. We present our recent results of the interface properties using this interface. As for InGaAs channels, we have also proposed a novel interfacial control technology utilizing InGaAs surface nitridation by ECR nitrogen plasma and successive post metallization annealing. This interfacial layer combined with an ECR sputtering SiO2 or an ALD Al2O3 gate insulator is shown to reduce Dit down to low order of 10 11 cm -2 eV -1 . The physical origin of this Dit reduction and the role of the nitridation are discussed.