Daejeong Kim

A Modified Dickson Charge Pump Circuit with High Efficiency and High Output Voltage

A power-efficient Dickson-based charge pump circuit is proposed and verified in this paper. Using a PMOS transfer switch in the new circuit solves the problem of the output voltage loss and its body control switch can suppress the parasitic bipolar action. Comparing this new one with the conventional circuit, the new circuit generates output voltage as high as 2.9VDD while the conventional one only 2VDD. For their efficiency values, the new circuit has better efficiency than the conventional one by as much as 14.5% with the area overhead of 12.2% using 3.5-μm and 40-V CMOS high-voltage process.

Negative charge pump circuit with large output current and high power efficiency

In this paper, we propose a new negative charge pump circuit which is based on the Dickson circuit. This circuit overcomes the limitation of the conventional Dickson pump circuit and doubler-based one such as large loss in output voltage, low power efficiency, and small output current. Comparing the new one with the conventional doubler-based circuit at the VDD=8V indicates the pumping time faster by 83.8%, 7 times larger output current, power efficiency better by 23.1%, and the layout area smaller by 15%. We have verified the new pump circuit using the commercial CMOS process with high-voltage devices.

Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V- V DD SRAM's

A new Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) scheme is proposed to suppress leakage current by two orders of magnitude in the SRAMs for sub-70 nm process technology with sub-1-V V DD [10]. Tiis two-order leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. In addition, metal shields are proposed to be inserted between the cell nodes and the bit lines not to allow the cell nodes to be flipped by the external bit-line coupling noise in this paper. A test chip has been fabricated to verify the effectiveness of the RRDSV scheme with the metal shields by using 0.18-μm CMOS process. The retention voltages of SRAMs with the metal shields are measured to be improved by as much as 40-60 mV without losing the stored data compared to the SRAMs without die shields.

Phase-shift self-oscillating class-D audio amplifier with multiple-pole feedback filter

A self-oscillating class-D audio amplifier employing a multiple-pole feedback filter is introduced intended for portable multimedia devices. As the oscillation is based on the Barkhausens criterion, the signal-dependent oscillation frequency is of great concern. Employing higher-order filters contributes to the stable oscillation frequency depending on the input amplitude as well as improves PSRR and THD. The concept is revealed comparatively with other works, and a design implemented in a 0.35um CMOS process under 3.3V supply is proposed and verified.

A spread-spectrum clock generator with direct VCO modulation in open-loop

A new topology is proposed to achieve a center-spreading SSCG. It employs a new spread filter, consisting of two capacitors and a resistor. The modulated triangular waveform is formed at the center of the control voltage coming from the segregated PLL. A definite advantage is that the spreading behavior does not affect the bandwidth of the PLL. Moreover, the modulation filter consumes smaller chip area because a larger resistor can be utilized for the required bandwidth.

Delay-based clock generator with edge transmission and reset

When a pulse transmits through delay stages, it dies out after all unless the rising and falling delays are perfectly matched. Alternatively, an edge can be transmitted through the new generateand-reset delay stages if properly reset in time. A new delay-based clock generator adopting the delay stages is proposed on that account. It is attractive in that the maximum operating frequency can be comparable to that of the ring oscillator. Furthermore, the reset of the pulse in the delay stage cleans out the random noise as well, inhibiting any noise residue phenomenon.

Analysis of switching frequency variation in self-oscillating class-D audio amplifiers

In this letter, a mathematical model in self-oscillating class-D audio amplifiers is proposed to describe the switching frequency variation as a fuction of the modulation depth. It is alleged in a very simple form which can be applied to any general structure adopting phase-shifting in the feedback filter, time delay of the loop, and the hysteresis window at the comparator. The main focus is set on the analysis of the phase-shifting filter which shows the least dependency on the modulation depth, which is not yet revealed.

Programmable pulsewidth control loop (PWCL) in dual-slope combination

A new technique to adjust the duty cycle of the output clock by adopting a pulsewidth control loop (PWCL) in dual-slope combination is presented. Correcting both rising and falling slopes simultaneously in their combination leads to a simple way for a wide correction range. Furthermore, the duty cycle can be easily adjusted to a desired value by setting up the programmable current sources in the charge pump. A generic circuit is suggested, and its validity is verified in a 0.13-μm CMOS technology under 1.2V supply. The simulated results with Spectre exhibit the integral nonlinearity (INL) of less than 2% for the output duty-cycle range from 6.25% to 93.75% with the consideration of process, voltage, and temperature (PVT) variation.

Multi-stage variable gain amplifier for low-voltage CCD analog-front end using CDA technique

A new technique adopting the correlated-double amplification (CDA) to improve the signal swing of the “linear-in-dB”variable gain amplifier (VGA) under a low-voltage supply is presented. This technique significantly reduces the finite op-amp gain requirement without compromising the speed. An efficient 3-stage VGA is introduced for the signal to swing up to 2/3 of the supply voltage by incorporating 2-stage push-pull op-amps. A design in a 0.13µm CMOS process under 1.2V supply is proposed and verified.