Hyun-Sun Mo

Low-Power

The conventional V_DD/3 write scheme is very advantageous in minimizing the unwanted resistance change in unselected cells during the write time. This is due to the fact that an amount of applied voltage at the unselected cells is reduced from V_DD/2 in the V_DD/2 scheme to V_DD/3 in the V_DD/3 scheme. However, the V_DD/3 scheme should sacrifice much larger switching power than the V_DD /2 scheme for having smaller voltage applied at the unselected cells. In this paper, we propose to combine the V_DD/3 scheme with the inversion coding circuit to alleviate large switching power of the V_DD/3 scheme. The proposed V_DD/3 scheme with the inversion coding circuit is verified for 500 × 500 and 1000 × 1000 passive memristor array with the operating frequency of 10 MHz to save power consumption as much as 19% than the conventional V_DD/3 scheme. For 50 MHz, the power saving is more improved to reach as much as 34%. In addition to this power saving, due to the reduced number of bit transitions in the inversion coding, the number of write cycles can be increased by as much as 39% thereby the poor endurance of complementary resistive switch array can be compensated significantly.

V_{\bf DD}

The drift of drain current (ID) in silicon nanowire field-effect transistor sensors is analyzed under various conditions of pHs and liquid gate voltages (VLG). It is found that H+ penetration into Helmholtz layer or sensing insulator is the cause of the current drift. To suppress the drift, a novel and fast measurement method with a two-step VLG is proposed and demonstrated. The drift could be completely suppressed by controlling the duration of the first step pulse. The time required to remove the ID drift is significantly reduced by the proposed method, from ~1200 s to below 100 s on average.

/3 Write Scheme With Inversion Coding Circuit for Complementary Memristor Array

Nanoscale memristors can be used as synapses in brain-mimicking neuromorphic systems. To act as synapses, memristors should be programmed or trained for the target synaptic weight values by applying a sequence of voltage pulses. In this paper, we show an implementation of FPGA-based training and recalling system of memristor synapses. Using the implemented FPGA-based training and recalling system of memristor synapses, we compare various pule modulation schemes which can be used in training and recalling memristor synapses. This comparison tells us that the pulse amplitude modulation is more suitable to train memristor synapses precisely than the others.

Drift-Free pH Detection With Silicon Nanowire Field-Effect Transistors

In this paper, the theory, circuit design, and possible applications of Cellular Nanoscale Networks (CNNs) which are based on memristor technology are reviewed. In the memristor-based CNNs, memristors can be used to realize the analog multiplication circuit that is essential in performing the computation functions of CNNs with low-power consumption and small area. Compared to the memristor-based crossbar architecture that can be used to mimic the fundamental neuron-cell-level operation such as Spike Time Dependent Plasticity (STDP), the memristor-based CNN circuit is more suitable in mimicking the advanced sensory systems such as image processing of humans retina. In this paper, we explain the basics of CNN computation at first and we discuss the previous memristor-based CNN circuits that are very useful in performing analog multiplication. And, also, we think of some practical issues of CNN circuits and discuss the possible solutions. For the CNN applications using memristors, we show the simulation results of CNN circuit with Laplacian template that can be used in the edge detection of various images.

FPGA-based training and recalling system for memristor synapses

We propose variable pumping frequency (VPF) scheme which is merged with the previous reconfigurable charge pump (RCP) circuit that can change its architecture according to a given sunlight condition. Here, merging the VPF scheme with the architecture reconfiguration can improve percentage output currents better by 21.4% and 22.4% than RCP circuit with the fixed pumping frequencies of 7 MHz and 15 MHz, respectively. Comparing the VPF scheme with real maximum power points (MPP), the VPF can deliver 91.9% of the maximum amount of output current to the load on average. In terms of the power and area overheads, the VPF scheme proposed in this paper consumes the power by 0.4% of the total power consumption and occupies the layout area by 1.61% of the total layout area.

Memristor-based cellular nanoscale networks: Theory, circuits, and applications

A self-oscillating class-D audio amplifier employing a multiple-pole feedback filter is introduced intended for portable multimedia devices. As the oscillation is based on the Barkhausens criterion, the signal-dependent oscillation frequency is of great concern. Employing higher-order filters contributes to the stable oscillation frequency depending on the input amplitude as well as improves PSRR and THD. The concept is revealed comparatively with other works, and a design implemented in a 0.35um CMOS process under 3.3V supply is proposed and verified.

Reconfigurable Charge Pump Circuit with Variable Pumping Frequency Scheme for Harvesting Solar Energy under Various Sunlight Intensities

Although the ion-sensitive field effect transistor (ISFET)-based biosensor has a great potential for point-of-care testing systems, the current drift still remains as a challenging issue for its commercialization. Furthermore, the drift makes the design of readout circuit for a high-resolution biosensor very complicated because it is very sensitive to the amount of ionic species in electrolyte or human serum. However, its chemical/physical origin in neither yet fully understood nor modeled for the circuit design and simulation. In this paper, the mechanism of current drift in ISFET was explained by short term reaction and long term reaction dependent on position of hydrogen ion. Besides, we proposed the analytical drift model of drain current and threshold voltage for different pH levels and various device sizes in the top-down processed SiNW ISFET. We believe that our result is potentially useful for the drift-aware circuit design for high-resolution biosensor system.

Phase-shift self-oscillating class-D audio amplifier with multiple-pole feedback filter

In this study, we investigated the effects of nanowire size on the current sensitivity of silicon nanowire (SiNW) ion-sensitive field-effect transistors (ISFETs). The changes in on-current (I on) and resistance according to pH were measured in fabricated SiNW ISFETs of various lengths and widths. As a result, it was revealed that the sensitivity expressed as relative I on change improves as the width decreases. Through technology computer-aided design (TCAD) simulation analysis, the width dependence on the relative I on change can be explained by the observation that the target molecules located at the edge region along the channel width have a stronger effect on the sensitivity as the SiNW width is reduced. Additionally, the length dependence on the sensitivity can be understood in terms of the resistance ratio of the fixed parasitic resistance, including source/drain resistance, to the varying channel resistance as a function of channel length.

Analysis and Modeling on the pH-Dependent Current Drift of Si Nanowire Ion-Sensitive Field Effect Transistor (ISFET)-Based Biosensors

A new topology is proposed to achieve a center-spreading SSCG. It employs a new spread filter, consisting of two capacitors and a resistor. The modulated triangular waveform is formed at the center of the control voltage coming from the segregated PLL. A definite advantage is that the spreading behavior does not affect the bandwidth of the PLL. Moreover, the modulation filter consumes smaller chip area because a larger resistor can be utilized for the required bandwidth.

Nanowire size dependence on sensitivity of silicon nanowire field-effect transistor-based pH sensor

The memristor ratioed logic (MRL)-based NAND operation is demonstrated using a combination of two Ag/γ-Fe2O3 nanoparticles assembly/Pt memristors in series with one CMOS inverter. This letter finds the MRL operational frequency to be restricted due to an inconsistency between SET and RESET and by an imbalance of the resistance between the two memristors. It is also shown that optical tuning resistance is a promising technique for use in improving the operational frequency of the MRL operation. MRL-based NAND logic demonstrated in this letter manifests itself as a potential candidate for memristor-based logic compatible with CMOS digital/analog circuitry.