Kyeong-Sik Min

Two-Step Write Scheme for Reducing Sneak-Path Leakage in Complementary Memristor Array

In this paper, a new two-step write scheme is proposed to minimize sneak-path leakage in complementary memristor (CM) array, where no selection device is needed. When R RESET/R SET = 100, the new two-step write scheme can increase the array size of CMs 10 times larger than the conventional write. If R RESET/R SET is increased to 500, we can increase the passive array size up to 1000 × 1000 with maintaining the read sensing margin lager than 10% of VDD. The two-step write scheme will be very essential in realizing passive cross-point array without any selection device that is known to be the ideal architecture for future 3-D memories.

Self-Adaptive Write Circuit for Low-Power and Variation-Tolerant Memristors

Memristive devices such as memristors that have been intensively studied for their possibilities as a strong candidate for future memories are known to have two problems. First, they need a large current in write operation, and second their process-V -temperature (PVT) variations are large compared with the conventional DRAM and FLASH memories. Moreover, the large writing current can be magnified with PVT variations. In this letter, a new write circuit is proposed to prevent unnecessary power loss by using a self-adjusting circuit for properly sizing the writing pulsewidth, thereby minimizing power consumption. The simulation results show that self-adjusting the pulsewidth can save power by 76% on average, compared to the conventional write circuit with a fixed pulsewidth.

Zero-Sleep-Leakage Flip-Flop Circuit With Conditional-Storing Memristor Retention Latch

In this paper, two new zero-sleep-leakage flip-flop (F-F) circuits are proposed to make the sleep leakage literally zero. At the sleep-in time, the F-Fs data are transferred to memristor retention latch; thus, the F-F can be completely cutoff from the external power supply saving the energy leak during the sleep time. The conditional storing circuit in the F-F (type-2) can reduce switching power by 87% in storing the data than the F-F (type-1). And, the crossover time of the F-F (type-2) is shortened by 97% than the F-F (type-1).

Neuromorphic crossbar circuit with nanoscale filamentary-switching binary memristors for speech recognition

In this paper, a neuromorphic crossbar circuit with binary memristors is proposed for speech recognition. The binary memristors which are based on filamentary-switching mechanism can be found more popularly and are easy to be fabricated than analog memristors that are rare in materials and need a more complicated fabrication process. Thus, we develop a neuromorphic crossbar circuit using filamentary-switching binary memristors not using interface-switching analog memristors. The proposed binary memristor crossbar can recognize five vowels with 4-bit 64 input channels. The proposed crossbar is tested by 2,500 speech samples and verified to be able to recognize 89.2% of the tested samples. From the statistical simulation, the recognition rate of the binary memristor crossbar is estimated to be degraded very little from 89.2% to 80%, though the percentage variation in memristance is increased very much from 0% to 15%. In contrast, the analog memristor crossbar loses its recognition rate significantly from 96% to 9% for the same percentage variation in memristance.

Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs

As a candidate for the clock-gating scheme, Zigzag Super Cut-off CMOS (ZSCCMOS) has been proposed to reduce not only the switching power but also the leakage power. Due to its fast wakeup nature, the ZSCCMOS can be best suited to the clock-gating scheme. The wakeup time of the ZSCCMOS is estimated to be 12 times faster than the conventional Super Cut-off CMOS (SCCMOS) in 70-nm process technology. From the measurement of wakeup time in 0.6-/spl mu/m technology, it is observed to be eight times faster than the conventional scheme. Layout area, power, and delay overhead of the ZSCCMOS are discussed and analyzed in this paper.

New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing

In this paper, we propose a new memristorbased crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.

PCRAM Flip-Flop Circuits with Sequential Sleep-in Control Scheme and Selective Write Latch

In this paper, two new flip-flop circuits with PCRAM latches that are FF-1 and FF-2, respectively, are proposed not to waste leakage during sleep time. Unlike the FF-1 circuit that has a normal PCRAM latch, the FF-2 circuit has a selective write latch that can reduce the switching activity in writing operation to save switching power at sleep-in moment. Moreover, a sequential sleep-in control is proposed to reduce the rush current peak that is observed at the sleep-in moment. From the simulation of storing ‘000000’ to the PCRAM latch, we could verify that the proposed FF-1 and FF-2 consume smaller power than the conventional 45-nm FF if the sleep time is longer than 465 μs and 95 μs, respectively, at 125°C. For the rush current peak, the sequential sleep-in control could reduce the current peak as much as 77%.

New Twin Crossbar Architecture of Binary Memristors for Low-Power Image Recognition With Discrete Cosine Transform

In this paper, we propose a new twin crossbar architecture of binary memristors for low-power image recognition. In the new twin crossbar, we use two identical memristor arrays instead of using the previous complementary memristor arrays of M+ and M-. Thereby, we can apply the discrete cosine transform (DCT) algorithm to reduce the number of low-resistance state (LRS) cells in the two identical M+ arrays. With the reduced number of LRS cells in two M+ arrays, the power consumption in the crossbar can be significantly saved compared to the previous complementary crossbar that is not suitable to DCT. When the number of discarded coefficients in the DCT matrix is 56.25%, 67.19%, 76.56%, and 84.38%, the power consumption of the new twin crossbar is reduced by 51.7%, 61.3%, 69.9%, and 77.4%, respectively, compared to the previous complementary one.

A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs

A new compact but accurate Verilog-A model for Multi-Level-Cell Phase-change RAMs is proposed in this paper. The previous circuit-based SPICE macromodel has to have a very complicated circuit to describe multi-level resistance thus it needs a long simulation time and occupies large computer memories. This new Verilog-A model can easily model the multi-level resistance by using the partial SET and RESET states where PCRAM resistance changes continuously without having a complicated circuit-based macromodel. Moreover, this new model is more portable, reliable, and simpler than the traditional C-based SPICE model owing to the advantage of Verilog-A. The new model has been compared with the measurement and proved to have good agreement with the measurement.

Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memorys current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristors current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.