Daewon Yang

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

Extremely thin SOI (ETSOI) MOSFET is a viable option for future CMOS scaling owing to superior short-channel control and immunity to random dopant fluctuation. However, challenges of ETSOI integration have so far hindered its adoption for mainstream CMOS. This is especially true for low-power applications, where SOI wafer cost is deemed to significantly add to the total cost. We have recently reported a novel integration scheme to overcome some of the major ETSOI manufacturing issues such as difficulty in doping thin silicon layer, process induced silicon loss, and the dilemma of reduction of external resistance and the increase of parasitic capacitance [1, 2]. The proposed integration flow significantly simplifies device processing and leads to considerable reduction in the number of critical masks [2].

Improving Yields of High Performance 65 nm Chips with Sputtering Top Surface of Dual Stress Liner

This paper presents a simple, effective, and economical method to improve the yield of high performance 65 nm SOI CMOS technology using dual stress nitride liner (DSL) for performance enhancement. Sputtering is used to reduce the complexity caused by DSL boundaries to smooth/trim the top surface of the DSL, which results into a significant yield increase. The perfect yield of 36 Mb 0.65 mum2 SRAM is increased by 25%. The yield for dual-core microprocessors is increased by 33% and for single-core microprocessors by 75%. Yield improvement is explained and sputtering effects on DSL stress and device performance are discussed. This method is in qualification process for product manufacturing.