Kaushik Chanda

Self-assembled near-zero-thickness molecular layers as diffusion barriers for Cu metallization

The present invention provides a diffusion barrier in an integrated circuit. The diffusion barrier comprises a self-assembled monolayer. The diffusion barrier is preferably less than 5 nm thick; more preferably it is less than 2 nm thick. The self-assembled monolayer typically contains an aromatic group at its terminus.

Line edge roughness and spacing effect on low-k TDDB characteristics

The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative format. This work reports a thorough investigation into the low-k SiCOH line LER effect on low-k TDDB covering both experimental results and finite element modeling (FEM) simulations. The maximum electric field intensity as a result of sidewall LER bump was found to depend on the bump curvature. The decrease of low-k line spacing that resulted in a shorter TDDB lifetime even under the same applied electric field was then carefully analyzed. A simple analytical model of the effect of line edge roughness on TDDB failure time reduction is presented. This model was verified by experimental results. Additionally, a method to electrically quantify an overall line edge roughness is introduced.

Physical, Electrical, and Reliability Characterization of Ru for Cu Interconnects

Thin film characterization, electrical performance, and preliminary reliability of physical vapor-deposited (PVD) TaN/chemical vapor-deposited (CVD) Ru bilayer were carried out to evaluate its feasibility as a liner layer for back-end of line (BEOL) Cu-low k integration. Adhesion and barrier strength were studied using 4-point bend, X-ray diffraction (XRD), and triangular voltage sweep (TVS) techniques. Electrical yields and line/via resistances were measured at both single and dual damascene levels, with PVD TaN/Ta liner layer as a baseline control. Reliability studies included electromigration (EM) and current-voltage (I-V) breakdown tests

Implications of a threshold failure time and void nucleation on electromigration of copper interconnects

Electromigration results are described for a dual damascene structure with copper metallization and a low-k dielectric material. The failure times follow a 3-parameter lognormal behavior, with a threshold failure time needed to represent the entire failure distribution. We found that the threshold failure time scales differently with current density from the median time to failure, which has significant implications for making reliability predictions. It is shown that the threshold failure time corresponds to damage (presumably voids) nucleation of the electromigration process. The observed current density dependency, along with scanning electron microscopy cross sections of stressed samples and Monte Carlo simulations of failure distributions, suggests that both void nucleation and void growth should be considered for accurate modeling of the electromigration lifetime.

Nondestructive electrical characterization of integrated interconnect line-to-line spacing for advanced semiconductor chips

Poor process controls may cause huge line spacing variation across a semiconductor wafer during back-end-of-the-line integration in advanced semiconductor integrated circuit fabrication. As a consequence, significant degradation in yield, performance, and reliability may be observed. Line spacing variation also imposes challenges for accurate time dependent dielectric breakdown reliability lifetime projection. In this paper, a nondestructive, fast electrical method for determining a line-to-line spacing of a semiconductor chip is proposed. The method includes experimentally determining a slope from capacitance measurement (kCA), experimentally determining a slope from current-voltage measurement (kSE), and finally determining a line-to-line spacing from the slope kCA and the slope kSE. The line-to-line spacing determined from this method shows an excellent agreement with constructional analysis data.

Extendibility of PVD barrier/seed for BEOL Cu metallization

The paper describes a new physical vapor deposition (PVD) metallization scheme that shows a better extendibility for future technology nodes as compared to the conventional scheme. In addition to reducing the thicknesses of both the diffusion barrier and the copper seed layer (Yang, C.-C. et al., MRS Adv. Metallization Conf., p.213, 2004), this new scheme also features a sacrificial process (also called barrier-first process) (Alers, G., IEEE Int. Interconnect Technology Conf., 2003), a via-punch through process (Edelstein, D. et al., IEEE Int. Reliability Physics Symp., p.316, 2004; Kuma, N. et al., MRS Adv. Metallization Conf, p.247, 2004) and a simultaneous preclean with a metal neutral deposition process (Yang et al., US Patent 6,784,105, 2004; Uzoh, C. et al., US Patents 5,930,669, 1999; 5,933,753, 1999; 6,429,519, 2002). Significant metal line and via contact resistance decrease was observed with equal or better reliability. The impact of a sputter etch integration scheme on electrical yield and reliability is also reported. The new sputter scheme decreases contact resistance at the via/interconnect interface and can offset the one resulting from dimension scaling and thus extends PVD metallization usefulness for future technologies.

A study of via depletion electromigration with very long failure times

Liner coverage in the via plays a critical role on via depletion EM for dual damascene Cu interconnects. Poor liner coverage at the via bottom often results in early EM fails. On the other hand, if the liner at via bottom is permeable to Cu diffusion, thanks to the constant Cu supply into the via from the line below, a very long or even “immortal” EM failure mode can be observed. This paper discusses how to modulate the Cu diffusion through the via bottom liner and its impact on product reliability.

Integration and reliability of CVD Ru cap for Cu/Low-k development

Selective CVD Ru cap deposition process has been developed for BEOL Cu/Low-k integration. Selectivity of CVD Ru deposition between Cu and dielectrics is investigated. Electrical performance, electromigration (EM) lifetime, voltage ramp (I–V), and time -dependent-dielectric-breakdown (TDDB) are also characterized for Cu interconnects capped with CVD Ru. This selective CVD Ru cap process is a good candidate for 22nm and beyond technology nodes.

A BEOL multilevel structure with ultra low-k materials (k ≤ 2.4)

A multilevel back-end-of-line structure with a dielectric constant k ≤ 2.4 ultra low-k materials was developed. k=3D2.2 ULK build was demonstrated at a 144nm wiring pitch and a k=3D2.4 ULK was demonstrated at a 288nm pitch. Good model-to-hardware correlation for the measured capacitance indicated no significant plasma damage to the ULK 2.2 material. The extracted copper resisitivity was consistent with size-effect predictions of an electron scattering model. An optimized SiN/SiCxNyH bilayer copper cap scheme was developed to minimize low-k damage. Also, an alternative CoWP metal cap, for improved electromigration resistance, is discussed. Preliminary TDDB reliability testing suggests Vbd of ULK 2.2 144nm pitch structures and ULK 2.4 288nm pitch structures was comparable to that of dense low-k films at similar pitches, with very few extrinsic fails.

From Process Assumptions to Development to Manufacturing

A tool has been developed that can be used to characterize or validate a BEOL interconnect technology. It connects various process assumptions directly to electrical parameters including resistance. The resistance of narrow copper lines is becoming a challenging parameter, not only in terms of controlling its value but also understanding the underlying mechanisms. The resistance was measured for 45nm-node interconnects and compared to the theory of electron scattering. This work will demonstrate how valuable it is to directly link the electrical models to the physical on-wafer dimensions and in turn to the process assumptions. For example, one can generate a tolerance pareto for physical and or electrical parameters that immediately identifies those process sectors that have the largest contribution to the overall tolerance. It also can be used to easily generate resistance versus capacitance plots which provide a good BEOL performance gauge. Several examples for 45nm BEOL will be given to demonstrate the value of these tools.