Daeyun Kim

An Enhanced Dynamic-Range CMOS Image Sensor Using a Digital Logarithmic Single-Slope ADC

Many kinds of wide-dynamic-range (DR) CMOS image sensors (CIS) have been developed, such as a multiple sampling, a multiple exposure technique, etc. However, those techniques have some drawbacks of noise increasing, large power consumption, and huge chip area. In this brief, a new digital logarithmic single-slope analog-to-digital converter (SS-ADC) with a digital counter is described. Since the proposed scheme is easily implemented with a simple algorithm, we can reduce power consumption and chip area drastically. Further, the logarithmic SS-ADC enhances the DR by 24 dB. The proposed ADC, which has been fabricated using a 0.13- μm CIS process, achieves a signal-to-noise-plus-distortion ratio of 57.6 dB at 50 kS/s.

A Low Power Dual CDS for a Column-Parallel CMOS Image Sensor

In this paper, a 320 × 240 pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung 0.13 ㎛ 1P4M CMOS process and used a 4T APS with a pixel pitch of 2.25 ㎛. The measured column fixed pattern noise (FPN) is 0.10 LSB.

A 10-b 500 MS/s CMOS Folding A/D Converter with a Hybrid Calibration and a Novel Digital Error Correction Logic

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 ㎚ 1P6M CMOS has a DNL of ±0.8 LSB and an INL of ±1.0 LSB. The measured SNDR is 52.34-㏈ and SFDR is 62.04-㏈c when the input frequency is 78.15 ㎒ at 500 MS/s conversion rate. The SNDR of the ADC is 7-㏈ higher than the same circuit without the proposed calibration. The effective chip area is 1.55 ㎟, and the power dissipates 300 ㎽ including peripheral circuits, at a 1.2/1.5 V power supply.

12-bit 80MSPS double folding/interpolation A/D converter

In this paper, a CMOS analog-to-digital converter (ADC) with a 12-bit 80 MSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a folding ADC with a double folding and interpolating structure. An even folding circuit technique for the high resolution and high speed ADC are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18 um 1-poly 6-metal CMOS technology. The active area is 1.6 mm2 and 195 mw at 1.8 V power supply. The DNL and INL are within plusmn4/plusmn4LSB, respectively. The measured result of SNDR is 46 dB, when Fin=1MHz at Fs=80 MHz.

A wide dynamic range CMOS image sensor based on a new gamma correction technique

Many kinds of wide dynamic range (WDR) CMOS Image Sensors (CIS) have been developed, such as a multiple sampling, a multiple exposure technique, and so on. However, those techniques have some drawbacks of noise increasing, large power consumption, and huge chip area. In this paper, a new Single-Slope ADC (SS-ADC) for gamma correction with a nonlinear counter is described. Since the proposed scheme is easily implemented with a simple algorithm, we can reduce power consumption and chip area drastically. Further, the new SS-ADC for gamma correction enhances the Dynamic Range (DR) by 24dB. The proposed ADC, which has been fabricated using a 0.13um CIS process, achieves a 57.6dB SNDR at 50kS/s.

Design of a 10-bit CMOS image sensor based on an 8-bit configurable hold-and-go counter

In this paper, a 320×240 pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain a 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column counter type, and the frame rate is approximately 40% faster than the double memories type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung 0.13μm 1P4M CMOS process and used a 4T APS with a pixel pitch of 2.25μm. The measured column fixed pattern noise (FPN) is 0.10 LSB.

A 10-b 500MS/s CMOS cascaded folding A/D converter with a hybrid calibration and a prevision error correction logic

In this paper, a 10-b 500MS/s A/D converter (ADC) with a hybrid calibration and a new error correction logic is discussed. The proposed ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. In order to overcome the disadvantage of offset error, at the open-loop amplifier, a hybrid self-calibration circuit is proposed. Further, a novel prevision digital error correction logic (DCL) for folding ADC is also described. The ADC prototype using 130nm 1P6M CMOS has a DNL of ±0.8LSB and an INL of ±1.0LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15MHz at 500MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is 1.55mm and the power dissipates 300mW including peripheral circuits at 1.2/1.5V power supply.

A digitally self-calibrated low-noise 7-bit folding A/D converter

In this paper, a low noise 65nm 1.2V 7-bit 1GSPS A/D converter with a digitally self-calibrated technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2 and its interpolation rate is 8. A digitally self-calibrated technique with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage, due to process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm2 and the power consumption is about 110mW with a 1.2V power supply. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.

A low noise 65nm 1.2V 7-bit 1GSPS CMOS folding A/D converter with a digital self-calibration technique

In this paper, a 65nm 1.2V 7-bit 1GSPS A/D converter with a self-calibration technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2, interpolation rate is 8. An offset self-calibration circuit with a feedback loop and a recursive digital code inspection is described. The offset self-calibration circuit reduces the variation of the offset voltage, due to process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm2 and the power consumption is about 110mW at 1.2V power supply. The measured SNDR is about 38.48dB when the input frequency is 250MHz at 1GHz sampling frequency. The measured SNDR is 3dB higher than the same ADC without any calibration.

Design of a 7-bit 1GSPS folding-interpolation A/D converter with self-calibration technique

In this paper, a 65nm 1.2V 7-bit 1GSPS A/D converter with a self-calibration technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2, interpolation rate is 8. An offset self-calibration circuit with a feedback loop and a recursive digital code inspection is described. The offset self-calibration circuit reduces the variation of the offset voltage, due to process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm2 and the power consumption is about 110mW with a 1.2V power supply. The measured SNDR is about 38.48dB when the input frequency is 250MHz at 1GHz sampling frequency. The measured SNDR is 3dB higher than the same ADC without any calibration.